Application and Implementation

Note

Information in the following application sections is not part of the 3PEAK’s component specification and 3PEAK does not

warrant its accuracy or completeness. 3PEAK’s customers are responsible for determining suitability of components for

their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The TPL720 is a series of 400-mA high PSRR, low-dropout linear regulators with low quiescent current. The following

application schematic shows a typical usage of the TPL720 series.

Typical Application

Figure 13 shows the typical application schematic of the TPL720 series.

Figure 13. TPL720 Series Application Schematic

(1) EN pin is only available in the 4-/5-pin package

Input Capacitor and Output Capacitor

3PEAK recommends adding a 1-μF or greater capacitor with a 0.1-μF bypass capacitor in parallel at the IN pin to keep the

input voltage stable. The voltage rating of the capacitors must be greater than the maximum input voltage.

To ensure loop stability, the TPL720 series requires an output capacitor with a minimum effective capacitance value of 2.2 μF.

3PEAK recommends selecting an X5R- or X7R-type 4.7 μF or larger ceramic capacitor with low ESR over temperature.

Both input capacitors and output capacitors must be placed as close to the device pins as possible.

Power Dissipation

During normal operation, the LDO junction temperature should not exceed 125°C. Use the below equations to calculate the

power dissipation and estimate the junction temperature.

The power dissipation can be calculated using Equation 1.

PD = VIN − VOUT × IOUT + VIN × IGND

(1)

The junction temperature can be estimated using Equation 2. θJA is the junction-to-ambient thermal resistance (See Section

Thermal Information).

TPL720 Series

400-mA Output,1-µA Ultra-Low Quiescent Current LDO

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