EVAL-AD7760/AD7762EDZ

Rev. PrB | Page 4 of 23

LINK OPTIONS

The link options on the evaluation board should be set for the required operating setup before using the board. The functions of these

links are described in Table 1.

Table 1. Link Options

Link No.

Function

Position Descriptions

Default

LK1

Selects the VDD voltage for

Clock Buffers U16 and U2.

Position A selects VDD = 5 V. Achieves maximum performance.

Position B selects VDD = 2.5 V

Position A

R9, R10,

R13

A 0 Ω link must be placed in

either R9 or R10 to select the

MCLK source for the

AD7760/AD7762 device.

R13 must be in place to link the

MCLK signal to the EVAL-CED1Z

board to allow for data

acquisition using the supplied

software.

R9 routes the buffered 40 MHz on-board crystal oscillator to the MCLK pin of

the AD7760/AD7762 device.

R10 allows the user to input an external MCLK signal through the MCLK SMB

connector (J8), which is buffered (by U2) and routed to the MCLK pin of the

AD7760/AD7762 device.

R9 and

R13.