3

Cortex-M0+ Components

NVIC features

1, 2, 4, 8, 16, 24, or 32 external interrupt inputs, each with four levels

of priority

Dedicated NMI input

Support for both level-sensitive and pulse-sensitive interrupt lines

Optional WIC providing ultra-low power sleep mode support

Optional debug support

Zero to four hardware breakpoints

Zero to two watchpoints

Program Counter Sampling Register (PCSR) for non-intrusive code profiling,

if at least one hardware data watchpoint is implemented

Single step and vector catch capabilities

Support for unlimited software breakpoints using BKPT instruction

Non-intrusive access to core peripherals and zero-wait state system slaves

through a compact bus matrix. A debugger can access these devices, including

memory, even when the processor is running

Full access to core registers when the processor is halted

Optional, low gate-count CoreSight compliant debug access through a Debug

Access Port (DAP) supporting either Serial Wire or JTAG debug connections

Bus interfaces

Single 32-bit AMBA-3 AHB-Lite system interface that provides simple

integration to all system peripherals and memory

Single 32-bit slave port that supports the DAP

Interfaces

AHB-Lite interface

Transactions on the AHB-Lite interface are always marked as non-sequential.

Processor accesses and debug accesses share the external interface to external

AHB peripherals. The processor accesses take priority over debug accesses.

Any vendor specific components can populate this bus.

Debug Access Port

The processor has a low gate count DAP. This provides a Serial Wire or JTAG

debug port and connects to the processor slave port to provide full system-level

debug access.