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Arm Cortex-M0 Processor Datasheet

Datasheet

Figure 1:

Block diagram of the

Cortex-M0 processor

Overview

The Cortex-M0 processor has an exceptionally small silicon area, low power and minimal code

footprint, enabling developers to achieve 32-bit performance at an 8-bit price point, bypassing

the step to 16-bit devices. The ultra-low gate count of the processor enables

its deployment in analog and mixed signal devices.

Features

Feature

Description

Architecture

Armv6-M

Pipeline

3-stage

Bus Interface

AMBA AHB-Lite (Von Neumann bus architecture)

Interrupts

Non-maskable Interrupt (NMI) and up to 32 physical interrupts

Wake-up Interrupt

Controller (WIC)

Optional for waking up the processor from state retention power

gating or when all clocks are stopped

Sleep Modes

Integrated Wait For Interrupt (WFI) and Wait For Event (WFE)

instructions and Sleep On Exit capability

Sleep and Deep Sleep signals

Optional retention mode with

Arm Power Management Kit

Enhanced Instructions

Hardware single-cycle (32x32) multiply

Debug

Optional JTAG and Serial Wire Debug ports

Up to four breakpoints and two watchpoints

-M0

Nested vectored

interrupt controller

CORTEX®-M0

Nested vectored

interrupt controller

CPU

Armv6-M

AHB-Life

JTAG

Serial wire

Data

Watchpoint

Breakpoint

Unit

About the Processor

The Cortex-M0 processor is a configurable, multistage, 32-bit RISC processor. It has

an AMBA AHB-Lite interface and includes a Nested Vectored Interrupt Controller

(NVIC) component. It also has optional hardware debug functionality. The processor

can execute Thumb code and is compatible with other Cortex-M profile processors.