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Cortex-M4 Components

Processor

The Cortex-M4 processor features a low gate count processor core, with low latency

interrupt processing that has:

A subset of the Thumb instruction set, defined in the Armv7-M architecture

Banked Stack Pointer (SP)

Hardware divide instructions, SDIV and UDIV

Handler and Thread modes

Thumb and Debug states

Support for interruptible-continued instructions LDM, STM, PUSH, and POP

for low interrupt latency

Automatic processor state saving and restoration for low latency Interrupt Service

Routine (ISR) entry and exit

Support for Armv6 big-endian byte-invariant or little-endian accesses

Support for Armv6 unaligned accesses

Floating Point Unit (FPU) in the Cortex-M4 with FPU processor providing:

32-bit instructions for single-precision (C float) data-processing operations

Combined Multiply and Accumulate instructions for increased precision (Fused MAC)

Hardware support for conversion, addition, subtraction, multiplication with optional

accumulate, division, and square root

Hardware support for denormals and all IEEE rounding modes

32 dedicated 32-bit single precision registers, also addressable as 16

double-word registers

Decoupled three-stage pipeline

Nested Vectored Interrupt Controller

Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core

to achieve low latency interrupt processing. Features include:

External interrupts, configurable from 1 to 240

Bits of priority, configurable from 3 to 8

Dynamic reprioritization of interrupts

Priority grouping

— This enables selection of preempting interrupt levels and non preempting

interrupt levels.

Support for tail-chaining and late arrival of interrupts

— This enables back-to-back interrupt processing without the overhead of state

saving and restoration between interrupts.