5

Bus interfaces

Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, DCode,

and System bus interfaces

Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface

Bit-band support that includes atomic bit-band write and read operations

Memory access alignment

Write buffer for buffering of write data

Exclusive access transfers for multiprocessor systems

Debug port AHB-AP interface

The processor contains an Advanced High-performance Bus Access Port (AHB-AP) interface

for debug accesses. An external Debug Port (DP) component accesses this interface.

The Cortex-M4 system supports three possible DP implementations:

Serial Wire JTAG Debug Port (SWJ-DP)

— The SWJ-DP is a standard CoreSight debug port that combines JTAG-DP

and Serial Wire Debug Port (SW-DP).

SW-DP

— This provides a two-pin interface to the AHB-AP port.

No DP present

— If no debug functionality is present within the processor, a DP is not required.

The two DP implementations provide different mechanisms for debug access

to the processor. Your implementation must contain only one of these components. 

Figure 3: Cortex-M4

processor pipeline

Cortex-M4 Pipeline