4

Processor state automatically saved on interrupt entry, and restored on interrupt exit,

with no instruction overhead

Optional Wake-up Interrupt Controller (WIC), providing ultra-low power sleep

mode support

Memory Protection Unit (MPU)

An optional MPU for memory protection, including:

Eight memory regions

Sub Region Disable (SRD), enabling efficient use of memory regions

The ability to enable a background region that implements the default memory

map attributes

Cross Trigger Interface Unit

The optional CTI enables the debug logic and the Embedded Trace Macrocell (ETM)

to interact with each other and with other CoreSight components.

Debug and Trace

Low-cost debug solution that features:

Debug access to all memory and registers in the system, including access to memory

mapped devices, access to internal core registers when the core is halted, and access

to debug control registers even while SYSRESETn is asserted

Serial Wire Debug Port (SW-DP) or Serial Wire JTAG Debug Port (SWJ-DP) debug

access, or both

Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints

and code patches

Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints,

data tracing, and system profiling

Optional Instrumentation Trace Macrocell (ITM) for support of printf style debugging

Optional Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer (TPA),

including Single Wire Output (SWO) mode

Optional ETM for instruction trace

ETM interface

The ETM interface enables simple connection of an ETM to the processor. It provides a

channel for instruction trace to the ETM.

AHB Trace Macrocell interface

The AHB Trace Macrocell (HTM) interface enables a simple connection of the AHB trace

macrocell to the processor. It provides a channel for the data trace to the HTM.

Your implementation must include this interface to use the HTM interface. You must

set TRCENA to 1 in the Debug Exception and Monitor Control Register (DEMCR) before

you enable the HTM to enable the HTM port to supply trace data.