ADE9113 datasheet(53/55 Pages) AD

53 / 55 page

Data Sheet

ADE9103/ADE9112/ADE9113

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Rev. A | 53 of 55

Table 20. Register Details (Continued)

Addr

Name

Bits Bit Name

Settings Description

Reset Access

ISO_PHY_CRC_ERR

ISO PHY Error or Data Link CRC or Error Correcting Code

(ECC) Error Detected. An error was detected on NONISO to ISO

communications. No action necessary unless error repeatedly set.

0x0

R/W1C

ISO_EFUSE_MEM_ERR

ISO eFuse Memory Error. An uncorrectable eFuse error occurred

on the ISO die, and the die was automatically reinitialized. No

action necessary unless error repeatedly set.

0x0

R/W1C

ISO_DIG_MOD_V2_OVF

ISO Digital Modulator V2 Channel Overflow Detected. The

modulators on the ISO die are automatically reset.

0x0

R/W1C

ISO_DIG_MOD_V1_OVF

ISO Digital Modulator V1 Channel Overflow Detected. The

modulators on the ISO die are automatically reset.

0x0

R/W1C

ISO_DIG_MOD_I_OVF

ISO Digital Modulator Current Channel Overflow Detected on the

ISO Die. The modulators on the ISO die are automatically reset.

0x0

R/W1C

ISO_TEST_MMR_ERR

ISO Die Register Change Detected and Corrected. The watchdog

on the ISO die detected that a register value changed, and the

watchdog automatically corrected the change.

0x0

R/W1C

0x023

COM_FLT_TYPE

[7:3] RESERVED

Reserved.

0x0

ISO_STATUS_RD_ECC_E

ISO to NONISO Status Read Error Detected. An error was

detected on the transfer of status from the ISO die to NONISO

die. Single bit ECC errors are corrected. This field clears when the

STATUS0 register, COMFLT_ERR bit (Bit ) is written to 1.

0x0

ISO_PHY_ERR

PHY Error Detected on ISO to NONISO Communications.

An incorrect number of pulses was detected on the ISO

interface. This field clears when the STATUS0 register, Bit 0

(COMFLT_ERR) is written to 1.

0x0

ISO_ECC_ERR

ECC Error Detected on ISO to NONISO Communications. Note

that only single bit ECC errors are detected, and single bit errors

are also corrected. This field clears when the STATUS0 register,

Bit 0 (COMFLT_ERR) is written to 1.

0x0

0x024

COM_FLT_COUNT

[7:0] COM_FLT_COUNT

ECC or PHY Error Count on ISO to NONISO Communications.

This counter clears when the STATUS0 register, Bit 0

(COMFLT_ERR) is written to 1. The counter does not roll over

when it reaches 255.

0x0

0x025

CONFIG_CRC

[7:2] RESERVED

Reserved.

0x0

CRC_DONE

CRC Done Flag. Indicates that CRC recalculation initiated

by a CRC_FORCE has completed. Or, if a scheduled CRC

recalculation has yielded n updated CRC flag, this flag asserts.

0x0

R/W1C

CRC_FORCE

Force Background Register Map CRC Recalculation.

Automatically clears when CRC recalculation completes.

0x0

R/W

0x026

I_WAV_HI

[7:0] I_WAV[23:16]

ADC Current Channel Waveform Data.

0x0

R/W

0x027

I_WAV_MD

[7:0] I_WAV[15:8]

ADC Current Channel Waveform Data.

0x0

R/W

0x028

I_WAV_LO

[7:0] I_WAV[7:0]

ADC Current Channel Waveform Data.

0x0

R/W

0x029

V1_WAV_HI

[7:0] V1_WAV[23:16]

ADC V1 Channel Waveform Data.

0x0

R/W

0x02A

V1_WAV_MD

[7:0] V1_WAV[15:8]

ADC V1 Channel Waveform Data.

0x0

R/W

0x02B

V1_WAV_LO

[7:0] V1_WAV[7:0]

ADC V1 Channel Waveform Data.

0x0

R/W

0x02C

V2_WAV_HI

[7:0] V2_WAV[23:16]

ADC V2 Channel Waveform Data. The value of this register is

always 0x0 on the ADE9112.

0x0

R/W

0x02D

V2_WAV_MD

[7:0] V2_WAV[15:8]

ADC V2 Channel Waveform Data. The value of this register is

always 0x0 on the ADE9112.

0x0

R/W

0x02E

V2_WAV_LO

[7:0] V2_WAV[7:0]

ADC V2 Channel Waveform Data. The value of this register is

always 0x0 on the ADE9112.

0x0

R/W

0x075

UNIQUE_PART_ID_5

[7:0] UNIQUE_PART_ID[47:40]

Unique Part ID.

0xX1

0x076

UNIQUE_PART_ID_4

[7:0] UNIQUE_PART_ID[39:32]

Unique Part ID.

0xX1

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