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ADE9113 Datasheet(PDF) 28 Page - Analog Devices |
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ADE9113 Datasheet(HTML) 28 Page - Analog Devices |
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28 / 55 page  Data Sheet ADE9103/ADE9112/ADE9113 THEORY OF OPERATION analog.com Rev. A | 28 of 55 pull-up resistor. In this configuration, a single pin on the host can sense if any one of the connected ADCs has generated an interrupt. The MASK0 registers configures what events within the STATUS0 register trigger the IRQ pin. The MASK1 register configures what events within the STATUS1 register trigger the STATUS1X bit in the STATUS0 register. Similarly, the MASK2 register configures which events in STATUS2 trigger the STATUS2X bit in the STATUS0 register, which means that with the combination of MASK0, MASK1 and MASK2, any bit from the STATUS0, STATUS1, and STATUS2 registers can trigger the IRQ pin. The RESET_DONE interrupt is nonmaskable and always triggers the IRQ pin. The EFUSE_MEM_ERR bit within the STATUS0 reg- ister is another example of a nonmaskable bit. The bits within STATUS2 can be masked with the MASK2 register because all of those faults cause action on the ISO side such as reset. |
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