TC9329AFAG datasheet(9/83 Pages) TOSHIBA

9 / 83 page

TC9329AFAG/AFCG

2006-03-02

Pin No.

Symbol

Pin Name

Function and Operation

Remarks

OSCin

local oscillation

signal input

For FM input, mode can be switched

between 1/2

+ Pulse Swallow VHF and

FM mode. For AM input, mode can be

switched between Pulse Swallow (HF)

and Direct Dividing (LF) mode.

Normally, local oscillation output

(Voltage-Controlled Oscillator: VCO

output) of 80 to 230 MHz is input in

VHF mode; 60 to 130 MHz in FM mode;

1 to 30 MHz in HF mode; 0.5 to 8 MHz

in LF mode.

A PLL can be configured using an

external prescaler. In such a case, set

the pin to LF, and connect the prescaler

divider output to the OSCin input pin

and the PSC input to the P2-3 (PSC)

output pin.

With an input amp incorporated,

capacitive-coupling, small-amplitude

operation is supported.

Note: The input is at high impedance in

PLL Off mode.

DO/OT

Phase comparator

output/output port

PLL phase comparator output pins.

Tristate output. When the program

counter divider output is higher than the

reference frequency, H level is output;

when lower, L level; and when they

match, high impedance. For the phase

comparator power supply, a 1.5-V

constant voltage supply (Vreg pin) is

used. Even if the power supply voltage

drops, a stable PLL can be configured.

The DO/OT pin can be programmed to

high impedance or as an output port

(OT).

Note: For tristate output, the H-level

output uses a constant voltage

supply. When H-level output

current is required, Toshiba

recommend using an external

power supply.

Vreg

Phase comparator

constant voltage

supply

Phase comparator constant voltage

supply.

When the phase comparator output is

tristate output, a constant voltage

supply of 1.5 V (typ.) is output to the

pin. For this output, connect a

stabilizing capacitor (0.47

µF typ.).

Constant voltage On/Off can be

programmed.

Because half the voltage potential can

be switched to AD converter A/D input,

it can be used to detect how much

battery remains.

At PLL operation, the constant voltage

is used for H level phase comparator

output. Thus, when H level output

current is required, Toshiba

recommend using an external power

supply. Externally apply 1.8 to 3.6 V to

the pin.

RESET

Reset input

Input pin for system reset signals.

RESET takes place at low level; at

high level, the program starts from

address “0”.

Vreg

VDD

RfIN1

Vreg

TC9329AFAG Datasheet(PDF) 9 Page - Toshiba Semiconductor

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