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TC9329AFAG Datasheet(PDF) 21 Page - Toshiba Semiconductor |
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TC9329AFAG Datasheet(HTML) 21 Page - Toshiba Semiconductor |
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21 / 83 page  TC9329AFAG/AFCG 2006-03-02 21 I/O Map (IN1 (M, C), IN2 (M, C), IN3 (M, C), OUT1 (M, C), OUT2 (M, C), OUT3 (M, C)) φL1 φL2 φL3 φK1 φK2 φK3 OUT1 OUT2 OUT3 IN1 IN2 IN3 I/O Code Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Power control I/O port 1 pull-down I/O port 1 IF monitor A/D data I/O port 1 0 HF PW0 PW1 FM PD0 K1 PD2 PD3 -0 -1 -2 -3 BUSY MANUAL OVER 0 AD0 AD1 AD2 AD3 -0 -1 -2 -3 Programmable counter 1 A/D control I/O port 2 IF data 1 A/D data I/O port 2 1 P0 P1 P2 P16 AD SEL0 AD SEL1 AD SEL2 STA -0 -1 -2 -3 F0 F1 F2 F3 AD4 AD5 BUSY 0 -0 -1 -2 -3 Programmable counter 2 Serial interface control 1 I/O port 3 IF data 2 I/O port 3 2 P4 P5 P6 P7 edge INV - SCK /O I - SCK SIO-ON -0 -1 -2 -3 F4 F5 F6 F7 -0 -1 -2 -3 Programmable counter 3 Serial interface control 2 I/O port 4 IF data 3 Serial interface monitor I/O port 4 3 P8 P9 P10 P11 STA O I/ - SO bit 4 8/ SIO Select -0 -1 -2 -3 F8 F9 F10 F11 BUSY COUNT SIO F/F 0 -0 -1 -2 -3 Programmable counter 4 Serial interface output data 1 I/O port 5 IF data 4 Serial interface input data 1 I/O port 5 4 P12 P13 P14 P15 SO0 SO1 SO2 SO3 -0 -1 -2 -3 F12 F13 F14 F15 SI0 SI1 SI2 SI3 -0 -1 -2 -3 Reference select Programmable counter Serial interface output data 2 IF data 5 Serial interface input data 2 5 R0 R1 R2 P16 SO4 SO5 SO6 SO7 F16 F17 F18 F19 SI4 SI5 SI6 SI7 IF counter control 1 Timer reset Test port 2 Timer 6 2 IF1/ PW INTR1 IF1/ IN2 IF2/ 2 Hz F/F Clock CKSTP mode #4 2 Hz F/F 10 Hz 100 Hz 0 IF counter control 2 Interrupt control I/O port 8 Interrupt master flag I/O port 8 7 STP STA/ MANIAL G0 G1 POL1 (INTR1) POL2 (INTR2) IE * -0 -1 -2 -3 HOLD INTR1 INTR2 0 IMF 0 0 0 -0 -1 -2 -3 MUTE control Interrupt permission flag I/O port 9 MUTE control Interrupt permission flag I/O port 9 8 MUTE I/O-1 POL HOLD EF1 (INTR1) FE2 (INTR2) FE3 (SIO) FE4 (Timer) -0 -1 -2 -3 MUTE I/O POL HOLD EF1 EF2 EF3 EF4 -0 -1 -2 -3 UNLOCK Detection DO2 control Interrupt latch reset Unlock detection Input port Interrupt latch 9 RESET PN M0 M1 ILR1 (INTR1) ILR2 (INTR2) ILR3 (SIO) ILR4 (Timer) HOLD PLL off control IF counter Split Prescaller IN PSC ENA F/F ENA (INTR1) IN2 IL1 IL2 IL3 IL4 BUZZR output control 1 Timer counter Interrupt detection data1 Timer counter data 1 A BF0 BF1 BF2 BEN ID0 ID1 ID2 ID3 DAL (DATA) → DA OT Count Up port 1 Pull-up CT0 CT1 CT2 CT3 DAL 0 0 0 BUZZR output control 2 Timer counter Interrupt detection data2 DAL address Timer counter data 2 DAL address B BM0 BM1 BUZR ON POL ID4 ID5 ID6 ID7 DA0 DA1 DA2 DA3 CT4 CT5 CT6 CT7 DA0 DA1 DA2 DA3 Timer counter control Data register 1 Data register 1 C CA Flag * * * CK0 CK1 GT CR d0 d1 d2 d3 CA flag 0 0 0 d0 d1 d2 d3 G register 1 Data select Data register 2 G register 1 Data select Data register 2 D G0 G1 G2 G3 SEL1 SEL2 SEL4 SEL8 d4 d5 d6 d7 G0 G1 G2 G3 S1 S2 S3 S4 d4 d5 d6 d7 G register 2 Segment data 1/ General purpose output data Data register 3 G register 2 Data register 3 E G4 G5 * * COM1/OT COM2/OT COM3/OT COM4/OT d8 d9 d10 d11 G4 G5 0 0 d8 d9 d10 d11 Test port 1 Segment data2/ Segment IO control Data register 4 Data register 4 F #0 #1 #2 #3 COM1 COM2 COM3 COM4 d12 d13 d14 d15 d12 d13 d14 d15 Refer to next page |
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