EP3C5 datasheet(65/348 Pages) ALTERA

65 / 348 page

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

5–5

Clock Networks

December 2011

Altera Corporation

Cyclone III Device Handbook

Volume 1

Figure 5–1 shows the clock control block.

Each PLL generates five clock outputs through the c[4..0] counters. Two of these

clocks can drive the GCLK through a clock control block, as shown in Figure 5–1.

f For more information about how to use the clock control block in the Quartus® II

software, refer to the Clock Control Block (ALTCLKCTRL) Megafunction User Guide.

Figure 5–1. Clock Control Block

Notes to Figure 5–1:

(1) The clkswitch signal can either be set through the configuration file or dynamically set when using the manual PLL switchover feature. The

output of the multiplexer is the input clock (fIN) for the PLL.

(2) The clkselect[1..0] signals are fed by internal logic and is used to dynamically select the clock source for the GCLK when the device is in user

mode.

(3) The static clock select signals are set in the configuration file. Therefore, dynamic control when the device is in user mode is not feasible.

(4) You can use internal logic to enable or disable the GCLK in user mode.

CLKSWITCH (1)

Static Clock Select (3)

Static Clock

Select (3)

Internal Logic

Clock Control Block

DPCLK or CDPCLK

CLKSELECT[1..0] (2)

Internal Logic (4)

inclk1

inclk0

CLK[n + 3]

CLK[n + 2]

CLK[n + 1]

CLK[n]

fIN

PLL

Global

Clock

Enable/

Disable

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