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Chapter 3: Memory Blocks in the Cyclone III Device Family

Overview

Cyclone III Device Handbook

December 2011

Altera Corporation

Volume 1

Byte Enable Support

The Cyclone III device family M9K memory blocks support byte enables that mask

the input data so that only specific bytes of data are written. The unwritten bytes

retain the previous written value. The wren signals, along with the byte-enable

(byteena) signals, control the write operations of the RAM block. The default value of

the byteena signals is high (enabled), in which case writing is controlled only by the

wren

signals. There is no clear port to the byteena registers. M9K blocks support byte

enables when the write port has a data width of ×16, ×18, ×32, or ×36 bits.

Byte enables operate in one-hot manner, with the LSB of the byteena signal

corresponding to the least significant byte of the data bus. For example, if

byteena = 01

and you are using a RAM block in ×18 mode, data[8..0] is enabled

and data[17..9] is disabled. Similarly, if byteena = 11, both data[8..0] and

data[17..9]

are enabled. Byte enables are active high.

Table 3–2 lists the byte selection.

Figure 3–2 shows how the wren and byteena signals control the RAM operations.

Table 3–2. byteena for Cyclone III Device Family M9K Blocks (1)

byteena[3..0]

Affected Bytes

datain

× 16

datain

× 18

datain

× 32

datain

× 36

[0] = 1

[7..0]

[8..0]

[7..0]

[8..0]

[1] = 1

[15..8]

[17..9]

[15..8]

[17..9]

[2] = 1

—

[23..16]

[26..18]

[3] = 1

—

[31..24]

[35..27]

Note to Table 3–2:

(1) Any combination of byte enables is possible.

Figure 3–2. Cyclone III Device Family byteena Functional Waveform (1)

inclock

wren

address

data

q (asynch)

XXXX

doutn

ABFF

FFCD

ABCD

ABFF

FFCD

ABCD

byteena

XXXX

ABCD

FFFF

ABFF

FFCD

contents at a0

contents at a1

contents at a2

rden

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