SM9503A

NIPPON PRECISION CIRCUITS INC.—3

BLOCK DIAGRAM

PIN DESCRIPTION

Pad

number

Pin number

Name

1. I: input, O: output, Ipu: input with pull-up resistor, –: supply pin

2. A: analog signal, D: digital signal

Description

1

7

XI

I

A

Crystal filter input connection

2

8

LF

O

A

Rectifier LPF capacitor connection

3

9

CB

O

A

Bottom-hold detector capacitor connection

4

10

CP

O

A

Peak-hold detector capacitor connection

5

11

HLDN

Ipu

D

AGC gain hold control (active LOW)

6

12

VSS

−

A(

−) Negative supply input (substrate potential)

7

13

OUT

O

D

Time code output (active LOW)

8

14

PON

Ipu

D

Standby-mode control input (active LOW)

9

15

VDD

−

A(

+) Positive supply input

10

−

VDDA

−

A(

+) Positive supply input (AGC amplifier)

11

16

IN2

I

A

Antenna input 2

12

1

NC

××

No connection (must be open)

13

2

IN1

I

A

Antenna input 1

14

3

NC

××

No connection (must be open)

15

4

VSSA

−

A(

−) Negative supply input (AGC amplifier)

16

5

XO1

O

A

Crystal filter output 1

17

6

XO2

O

A

Crystal filter output 2

VDDA

VSS

VDD

CP

AGC Control

Peak/Bottom

Hold Det.

Decoder

CB

HLDN

XI

OUT

LF

XO1

VSSA

IN1

IN2

XO2

LPF

Rectifier

Post Amp

AGC Amp

PON

Bias