Data Sheet

LT7170/LT7170-1

APPLICATIONS INFORMATION

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Rev. A | 21 of 36

USING RESISTOR CONFIGURATION PINS

The LT7170/LT7170-1 have two resistor configuration pins,

VOUT_CFG and PWM_CFG, and each uses a single ±1% resistor

to select key operating parameters. The resistors on the config-

uration pins are measured upon power-up and execution of a

RESTORE_USER_ALL or MFR_RESET command.

SETTING OUTPUT VOLTAGE

The VOUT_COMMAND command specifies the output voltage

when the regulator is enabled.

VOUT_COMMAND can be initialized using a resistor connected

between the VOUT_CFG pin and the PGND or SGND pin based

on the values in Table 7. If the VOUT_CFG pin is open or tied to

VDD18, the VOUT_COMMAND command is loaded from the NVM to

set the output voltage.

The following commands are initialized based on a percentage of

the VOUT_COMMAND command if the resistor configuration pins

are used to initialize the output voltage:

►

VOUT_OV_FAULT_LIMIT: 10%

►

VOUT_OV_WARN_LIMIT: 7.5%

►

VOUT_MAX: 7.5%

►

VOUT_MARGIN_HIGH: 5%

►

VOUT_MARGIN_LOW: −5%

►

VOUT_UV_WARN_LIMIT: −6.5%

►

VOUT_UV_FAULT_LIMIT: −7%

Table 7. VOUT_CFG Pin Configuration Resistor Selection

Resistor Value

(±1%)

Output Voltage Set Point (V)1

VOUT Range

Effective Error Amplifier Gain

Regulator Enable2

Floating or VDD18

Initialized from the NVM (default

0.5 V)

Initialized from NVM

(default 0.4 V ≤ VOUT ≤

1.375 V)

Initialized from the NVM (default 300 μS)

Initialized from the NVM (default: regulator is

enabled if the RUN pin is asserted high)

124 kΩ

5

1.6 V ≤ VOUT ≤ 5.5 V

300 μS

Enabled if the RUN pin is asserted high

107 kΩ

3.3

1.6 V ≤ VOUT ≤ 5.5 V

300 μS

Enabled if the RUN pin is asserted high

93.1 kΩ

2.5

0.8 V ≤ VOUT ≤ 2.75 V

300 μS

Enabled if the RUN pin is asserted high

80.6 kΩ

1.8

0.8 V ≤ VOUT ≤ 2.75 V

300 μS

Enabled if the RUN pin is asserted high

69.8 kΩ

1.5

0.8 V ≤ VOUT ≤ 2.75 V

300 μS

Enabled if the RUN pin is asserted high

60.4 kΩ

1.35

0.8 V ≤ VOUT ≤ 2.75 V

300 μS

Enabled if the RUN pin is asserted high

51.1 kΩ

1.2

0.4 V ≤ VOUT ≤ 1.375 V 300 μS

Enabled if the RUN pin is asserted high

43.2 kΩ

1.1

0.4 V ≤ VOUT ≤ 1.375 V 300 μS

Enabled if the RUN pin is asserted high

36.5 kΩ

1.0

0.4 V ≤ VOUT ≤ 1.375 V 300 μS

Enabled if the RUN pin is asserted high

30.9 kΩ

0.9

0.4 V ≤ VOUT ≤ 1.375 V 300 μS

Enabled if the RUN pin is asserted high

25.5 kΩ

0.85

0.4 V ≤ VOUT ≤ 1.375 V 300 μS

Enabled if the RUN pin is asserted high

21 kΩ

0.8

0.4 V ≤ VOUT ≤ 1.375 V 300 μS

Enabled if the RUN pin is asserted high

16.5 kΩ

0.75

0.4 V ≤ VOUT ≤ 1.375 V 300 μS

Enabled if the RUN pin is asserted high

11.8 kΩ

0.7

0.4 V ≤ VOUT ≤ 1.375 V 300 μS

Enabled if the RUN pin is asserted high

6.65 kΩ

0.6

0.4 V ≤ VOUT ≤ 1.375 V 300 μS

Enabled if the RUN pin is asserted high

0 (SGND)

Initialized from the NVM (default

0.5 V)

Initialized from the NVM

(default 0.4 V ≤ VOUT ≤

1.375 V)

Initialized from the NVM (default 300 μS)

Disabled and the RUN pin is ignored

1 Output voltage set point is controlled by VOUT_COMMAND.

2 The PMBus ON_OFF_CONFIG command selects whether the RUN pin and/or the PMBus OPERATION command enables the regulator.