DS055 (v2.1 April 3, 2007

www.xilinx.com

1

Product Specification

1-800-255-7778

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Features

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6 ns pin-to-pin logic delays

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System frequency up to 208 MHz

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288 macrocells with 6,400 usable gates

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Available in small footprint packages

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144-pin TQFP (117 user I/O pins)

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208-pin PQFP (168 user I/O pins)

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256-pin BGA (192 user I/O pins)

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256-pin FBGA (192 user I/O pins)

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280-pin CSP (192 user I/O pins)

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Pb-free available for all packages

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Optimized for high-performance 3.3V systems

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Low power operation

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5V tolerant I/O pins accept 5V, 3.3V, and 2.5V

signals

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3.3V or 2.5V output capability

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Advanced 0.35 micron feature size CMOS

Fast FLASH™ technology

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Advanced system features

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In-system programmable

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Superior pin-locking and routability with

Fast CONNECT™ II switch matrix

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Extra wide 54-input Function Blocks

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Up to 90 product-terms per macrocell with

individual product-term allocation

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Local clock inversion with three global and one

product-term clocks

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Individual output enable per output pin with local

inversion

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Input hysteresis on all user and boundary-scan pin

inputs

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Bus-hold circuitry on all user pin inputs

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Full IEEE Standard 1149.1 boundary-scan (JTAG)

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Fast concurrent programming

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Slew rate control on individual outputs

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Enhanced data security features

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Excellent quality and reliability

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Endurance exceeding 10,000 program/erase

cycles

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20 year data retention

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ESD protection exceeding 2,000V

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Pin-compatible with 5V-core XC95288 device in the

208-pin HQFP package

WARNING: Programming temperature range of

TA = 0° C to +70° C

Description

The XC95288XL is a 3.3V CPLD targeted for high-perfor-

mance, low-voltage applications in leading-edge communi-

cations and computing systems. It is comprised of 16

54V18 Function Blocks, providing 6,400 usable gates with

propagation delays of 6 ns. See Figure 2 for architecture

overview.

Power Estimation

Power dissipation in CPLDs can vary substantially depend-

ing on the system frequency, design application and output

loading. To help reduce power dissipation, each macrocell

in a XC9500XL device may be configured for low-power

mode (from the default high-performance mode). In addi-

tion, unused product-terms and macrocells are automati-

cally deactivated by the software to further conserve power.

For a general estimate of ICC, the following equation may be

used:

ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP

+ 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f

where:

MCHS = # macrocells in high-speed configuration

PTHS = average number of high-speed product terms

per macrocell

MCLP = # macrocells in low power configuration

PTLP = average number of low power product terms per

macrocell

f = maximum clock frequency

MCTOG = average % of flip-flops toggling per clock

(~12%)

This calculation was derived from laboratory measurements

of an XC9500XL part filled with 16-bit counters and allowing

a single output (the LSB) to be enabled. The actual ICC

value varies with the design application and should be veri-

fied during normal system operation. Figure 1 shows the

above estimation in a graphical form. For a more detailed

discussion of power consumption in this device, see Xilinx

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XC95288XL High Performance

CPLD

DS055 (v2.1 April 3, 2007

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Product Specification

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