† All control inputs are protected by the CMOS protection network.

NOTES: A.All p substrates are connected to V DD.

B. Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = VSS

C. Signal-level range: VSS V

≤ is ≤ VDD

Control

VC†

VDD

VSS

VSS

n

n

p

Out

Vos

Control

Switch

In

n

p

Vis

CD4066B-Q1

SCHS383

– APRIL 2011

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

ORDERABLE

TOP-SIDE

TA

PACKAGE

PART NUMBER

MARKING

–40°C to 125°C

SOIC

– D

Reel of 2500

CD4066BQDRQ1

CD4066BQ

Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry

2

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Copyright

© 2011, Texas Instruments Incorporated

Product Folder Link(s) :CD4066B-Q1