DDC232C datasheet(11/35 Pages) TI2

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DDC232

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SBAS331D – AUGUST 2004 – REVISED APRIL 2010

Frequency Response

CONFIGURATION REGISTER

The frequency response of the DDC232 is set by the

Some aspects of device operation are controlled by

front-end integrators and is that of a traditional

the onboard configuration register. The DIN_CFG,

continuous time integrator, as shown in Figure 7. By

CLK_CFG, and RESET pins are used to write to this

adjusting

tINT, the user can change the 3dB

bandwidth and the location of the notches in the

CONV low and strobe RESET; see Figure 8. Then

response.

The

frequency

response

the

∆Σ

begin shifting in the configuration data on DIN_CFG.

converter that follows the front-end integrator is of no

Data are written to the configuration register most

consequence because the converter samples a held

significant bit first. The data are internally latched on

signal from the integrators. That is, the input to the

the falling edge of CLK_CFG. Partial writes to the

∆Σ converter is always a DC signal. Since the output

configuration register are not allowed—make sure to

of the front-end integrators are sampled, aliasing can

send all 12 bits when updating the register.

occur. Whenever the frequency of the input signal

Optional readback of the configuration register is

exceeds one-half of the sampling rate, the signal will

available immediately after the write sequence.

fold back down to lower frequencies.

During

readback,

the

12-bit

configuration

data

followed by a 4-bit revision ID and the test pattern are

shifted out on the DOUT pin on the rising edge of

DCLK.

NOTE: Wth Format = 1, the test pattern is 304 bits,

with only the last 72 bits non-zero. This sequence of

outputs is repeated twice for each DDC232 and

daisy-chaining is supported in configuration readback.

Table 5 shows the test pattern configuration during

readback.

Table

shows

the

timing

for

the

configuration register read and write operations.

Strobe CONV to begin normal operation.

Table 5. Test Pattern During Readback

TEST PATTERN

TOTAL

Format BIT

(Hex)

READBACK BITS

30F066012480F6h

512

Figure 7. Frequency Response

30F066012480F69055h

640

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