NB679, 28 V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO

NB679 Rev. 1.03

www.MonolithicPower.com

13

7/27/2017

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5 V Linear Regulator

There is a built-in 100 mA standby linear

regulator with a fixed output at 5 V, controlled by

ENLDO. The 5 V LDO is intended mainly for an

auxiliary 5 V supply for the notebook system

during standby mode.

Add a ceramic capacitor with a value between

4.7

μF and 22 µF placed close to the LDO pins to

stabilize the LDOs.

LDO Switch Over

When the output voltage becomes higher than

4.8 V (and the power good is ok), the internal

LDO is switched over to VOUT by the internal

MOSFET. This helps reduce the power loss from

the LDO.

Power Good (PG)

The NB679 has power good (PG) output used to

indicate whether the output voltage of the buck

regulator is ready. PG is the open drain of a

MOSFET. It should be connected to VCC or

another voltage source through a resistor (e.g.

100 k). After the input voltage is applied, the

MOSFET is turned on so that PG is pulled to

GND before SS is ready. After the FB voltage

reaches 95 percent of the REF voltage, PG is

pulled high after 750 µs. When the FB voltage

drops to 85 percent of the REF voltage, PG is

pulled low.

Over-Current Protection (OCP)

NB679 has cycle-by-cycle over-current limiting

control.

The

current-limit

circuit

employs

a

"valley" current-sensing algorithm. The part uses

the Rds(on) of the LS-FET as a current-sensing

element. If the magnitude of the current-sense

signal is above the current-limit threshold, the

PWM is not allowed to initiate a new cycle.

The trip level is fixed internally. The inductor

current is monitored by the voltage between GND

and SW. GND is used as the positive current

sensing node, so GND should be connected to

the source terminal of the bottom MOSFET.

Since the comparison is done during the HS-FET

off and LS-FET on state, the OC trip level sets

the valley level of the inductor current. Thus, the

load current at the over-current threshold (IOC)

can be calculated with Equation (2):



 inductor

OC

I

I

I _ limit

2

(2)

In an over-current condition, the current to the

load exceeds the current to the output capacitor;

thus, the output

voltage tends to fall off.

Eventually, it ends up crossing the under-voltage

protection threshold and shuts down. Fault

latching can be re-set by EN going low or the

power cycling of VIN.

Over/Under-Voltage Protection (OVP/UVP)

NB679 monitors the output voltage to detect over

and under voltage. Once the feedback voltage

becomes higher than 122 percent of the target

voltage, the OVP comparator output goes high,

and the circuit latches as the HS-FET driver turns

off, and the LS-FET driver turns on, acting as an

-1.8 A current source.

When the feedback voltage drops below 75

percent of the Vref but remains higher than 50

percent, the UVP-1 comparator output goes high.

The part is latched if the FB voltage remains in

this range for about 32 µs (latching the HS-FET

off and the LS-FET on). The LS-FET remains on

until the inductor current hits zero. During this

period, the valley current limit helps control the

inductor current.

When the feedback voltage drops below 50

percent of the Vref, the UVP-2 comparator output

goes high, and the part is latched off directly after

the comparator and logic delay (latching the HS-

FET off and the LS-FET on). The LS-FET

remains on until the inductor current hits zero.

Fault latching can be re-set by EN going low or

the power cycling of VIN.

UVLO Protection

The part starts up only when the Vin voltage is

higher than the UVLO rising threshold voltage.

The part shuts down when VIN is lower than the

Vin falling threshold. The UVLO protection is

non-latch off. Fault latching can be re-set by EN

going low or the power -cycling of VIN.

If an application requires a higher under-voltage

lockout (UVLO), use EN (see Figure 5) to adjust

the input voltage UVLO by using two external

resistors. It is recommended to use the enable

resistors to set the Vin falling threshold above 5.5

V.

The

rising

threshold

should

be