ADC14DS080 datasheet(4/35 Pages) TI2

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VDR

DRGND

AGND

ADC14DS080

SNAS428B – SEPTEMBER 2007 – REVISED APRIL 2013

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Pin Descriptions and Equivalent Circuits (continued)

Pin No.

Symbol

Equivalent Circuit

Description

This is a four-state pin controlling the input clock mode and output

data format.

OF/DCS = VA, output data format is 2's complement without duty

cycle stabilization applied to the input clock

OF/DCS = AGND, output data format is offset binary, without duty

cycle stabilization applied to the input clock.

OF/DCS

OF/DCS = (2/3)*VA, output data is 2's complement with duty cycle

stabilization applied to the input clock

OF/DCS = (1/3)*VA, output data is offset binary with duty cycle

stabilization applied to the input clock.

Note: This signal has no effect when SPI_EN is high and the SPI

interface is enabled.

This is a two-state input controlling Power Down.

PD = VA, Power Down is enabled and power dissipation is reduced.

PD_A

PD = AGND, Normal operation.

PD_B

Note: This signal has no effect when SPI_EN is high and the SPI

interface is enabled.

Test Mode. When this signal is asserted high, a fixed test pattern

(10100110001110 msb->lsb) is sourced at the data outputs

With this signal deasserted low, the device is in normal operation

TEST

mode.

Note: This signal has no effect when SPI_EN is high and the SPI

interface is enabled.

Word Alignment Mode.

In single-lane mode this pin must be set to logic-0.

In dual-lane mode only, when this signal is at logic-0 the serial data

WAM

words are offset by half-word. With this signal at logic-1 the serial

data words are aligned with each other.

Note: This signal has no effect when SPI_EN is high and the SPI

interface is enabled.

Dual-Lane Configuration. The dual-lane mode is selected when this

signal is at logic-0. With this signal at logic-1, all data is sourced on a

DLC

single lane (SD1_x) for each channel.

Note: This signal has no effect when SPI_EN is high and the SPI

interface is enabled.

Serial Clock. This pair of differential LVDS signals provides the serial

clock that is synchronous with the Serial Data outputs. A bit of serial

data is provided on each of the active serial data outputs with each

OUTCLK+

falling and rising edge of this clock. This differential output is always

OUTCLK-

enabled while the device is powered up. In power-down mode this

output is held in logic-low state. A 100-ohm termination resistor must

always be used between this pair of signals at the far end of the

transmission line.

Serial Data Frame. This pair of differential LVDS signals transitions

at the serial data word boundries. The SD1_A+/- and SD1_B+/-

output words always begin with the rising edge of the Frame signal.

The falling edge of the Frame signal defines the start of the serial

FRAME+

data word presented on the SD0_A+/- and SD0_B+/- signal pairs in

FRAME-

the Dual-Lane mode. This differential output is always enabled while

the device is powered up. In power-down mode this output is held in

logic-low state. A 100-ohm termination resistor must always be used

between this pair of signals at the far end of the transmission line.

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