LM3553

SNVS414B – FEBRUARY 2008 – REVISED MAY 2013

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CAPACITOR SELECTION

The LM3553 requires 2 external capacitors for proper operation (CIN = 10µF recommended (4.7µF min.) and

COUT = 10µF (single LED) or 4.7µF (series LEDs)). Surface-mount multi-layer ceramic capacitors are

recommended. These capacitors are small, inexpensive and have very low equivalent series resistance (ESR

<20m

Ω typ.). Tantalum capacitors, OS-CON capacitors, and aluminum electrolytic capacitors are not

recommended for use with the LM3553 due to their high ESR, as compared to ceramic capacitors.

For most applications, ceramic capacitors with X7R or X5R temperature characteristic are preferred for use with

the LM3553. These capacitors have tight capacitance tolerance (as good as ±10%) and hold their value over

temperature (X7R: ±15% over -55°C to 125°C; X5R: ±15% over -55°C to 85°C).

Capacitors with Y5V or Z5U temperature characteristic are generally not recommended for use with the LM3553.

Capacitors with these temperature characteristics typically have wide capacitance tolerance (+80%, -20%) and

vary significantly over temperature (Y5V: +22%, -82% over -30°C to +85°C range; Z5U: +22%, -56% over +10°C

to +85°C range). Under some conditions, a nominal 1µF Y5V or Z5U capacitor could have a capacitance of only

0.1µF. Such detrimental deviation is likely to cause Y5V and Z5U capacitors to fail to meet the minimum

capacitance requirements of the LM3553.

The recommended voltage rating for the input capacitor is 10V (min = 6.3V). For a single flash LED, the

recommended output capacitor voltage rating is 10V (min = 6.3V), and for series LEDs the recommended

voltage is 25V (min = closest voltage rating above the sum of (VLED × NLEDs) and VFB). The recommended

value takes into account the DC bias capacitance losses, while the minimum rating takes into account

the OVP trip levels.

SCHOTTKY DIODE SELECTION

The output diode must have a reverse breakdown voltage greater than the maximum output voltage. The diodes

average current rating should be high enough to handle the LM3553’s output current. Additionally, the diodes

peak current rating must be high enough to handle the peak inductor current. Schottky diodes are recommended

due to their lower forward voltage drop (0.3V to 0.5V) compared to ( 0.8V) for PN junction diodes.

LAYOUT CONSIDERATIONS

The WSON is a leadless package with very good thermal properties. This package has an exposed DAP (die

attach pad) at the underside center of the package measuring 1.86mm x 2.2mm. The main advantage of this

exposed DAP is to offer low thermal resistance when soldered to the thermal ground pad on the PCB. For good

PCB layout a 1:1 ratio between the package and the PCB thermal land is recommended. To further enhance

thermal conductivity, the PCB thermal ground pad may include vias to a 2nd layer ground plane. For more

detailed instructions on mounting WSON packages, please refer to Texas Instruments Application Note AN-1187

SNOA401.

The high switching frequencies and large peak currents make the PCB layout a critical part of the design. The

proceeding steps must be followed to ensure stable operation and proper current source regulation.

1. If possible, divide ground into two planes, one for the return terminals of COUT, CIN and the I

2C Bus, the other

for the return terminals of RSET. Connect both planes to the exposed DAP, but nowhere else.

2. Connect the inductor and the anode of D1(schottky) as close together as possible and place this connection

as close as possible to the SW pin. This reduces the inductance and resistance of the switching node which

minimizes ringing and excess voltage drops.

3. Connect the return terminals of the input capacitor and the output capacitor as close as possible to the

exposed DAP and through low impedance traces.

4. Bypass VIN with at least a 4.7µF ceramic capacitor. Connect the positive terminal of this capacitor as close

as possible to VIN.

5. Connect COUT as close as possible to the cathode of D1(schottky). This reduces the inductance and

resistance of the output bypass node which minimizes ringing and voltage drops. This will improve efficiency

and decrease the noiseinjected into the current sources.

6. Route the trace for RSET away from the SW node to minimize noise injection.

7. Do not connect any external capacitor to the RSET pin.

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