AFE0064

SLAS672 – SEPTEMBER 2009 ........................................................................................................................................................................................ www.ti.com

Contact TI sales for suitable ADC.

Figure 32. Typical Schematic Showing Four Channel ADC Interface with Two AFEs

RESETTING THE FPD PANEL

It is possible to reset the photo diodes using IRST. The integrator acts like a unity gain buffer during reset and

the device can source or sink 50 µA through each of the 64 input pins while in the reset phase. For example, to

reset a 10 pC charge it requires 10pC/50µA = 1/5 µSec.

Refer to Figure 3 for the reset timing details. The device is in the reset phase for 32/8 clocks after IRST rising

edge in sequential/simultaneous mode respectively. The reset duration is controlled by selecting a clock speed or

holding one of the 32/8 clocks for the required time in sequential/simultaneous mode respectively.

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