REF LEVEL

0.000 dB

0.0 deg

100

1k

START 50.000 Hz

10k

STOP 50 000.000 Hz

/DIV

10.000 dB

45.000 deg

0

GAIN

PHASE

REF LEVEL

0.000 dB

0.0 deg

100

1k

START 100.000 Hz

10k

STOP 100 000.000 Hz

/DIV

10.000 dB

45.000 deg

0

GAIN

PHASE

100k

21

LM5575-Q1

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SNOSB23F – OCTOBER 2008 – REVISED JULY 2019

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Typical Application (continued)

RLOAD = 5 Ω

COUT = 130 µF

Figure 18. Gain and Phase of Modulator

Components R4 and C5 configure the error amplifier as a type II configuration which has a pole at DC and a

zero at fZ = 1 / (2πR4C5). The error amplifier zero cancels the modulator pole and leaves a single pole response

at the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a very

stable loop with 90 degrees of phase margin.

For the design example, a target loop bandwidth (crossover frequency) of 15 kHz was selected. Select the

compensation network zero (fZ) at least an order of magnitude less than the target crossover frequency. This

constrains the product of R4 and C5 for a desired compensation network zero 1 / (2π R4 C5) to be less than 2

kHz. If the user increases R4 while they proportionally decrease C5, the error amp gain increases. Conversely, if

the user decreases R4 while proportionally they increase C5, the error amp gain decreases. For the design

example, C5 was selected for 0.01 µF and R4 was selected for 49.9 k

Ω. These values configure the

compensation network zero at 320 Hz. The error amp gain at frequencies greater than fZ is: R4 / R5, which is

approximately 10 (20 dB).

Figure 19. Error Amplifier Gain and Phase

The overall loop can be predicted as the sum (in dB) of the modulator gain and the error amp gain.