LMH0346

SNLS248J – APRIL 2007 – REVISED APRIL 2013

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PIN DESCRIPTIONS

HTSSOP

WQFN

Name

Description

Pin

Pin

1

24

LF1

Loop Filter.

2

1

LF2

Loop Filter.

3

2

RATE 0

Data Rate select input. This pin has an internal pulldown.

4

3

RATE 1

Data Rate select input. This pin has an internal pulldown.

5

4

SDI

Data Input True.

6

5

SDI

Data Input Complement.

7

6

VCC

Positive power supply.

Bypass/Auto Bypass mode select. Bypasses reclocking when high. This

8

7

BYPASS/AUTO BYPASS

pin has an internal pulldown.

Data and Clock Output Mute Input. Mutes the output when low. This pin

9

8

OUTPUT MUTE

has an internal pullup.

10

9

XTAL IN/EXT CLK

Crystal or External Oscillator Input.

11

12

XTAL OUT

Crystal Oscillator Output.

12

13

LOCK DETECT

PLL Lock Detect Output (active high).

13

14

SCO/SDO2

Serial Clock or Serial Data Output 2 Complement.

14

15

SCO/SDO2

Serial Clock or Serial Data Output 2 True.

15

16

VCCO

Positive power supply (Output Driver).

16

17

SDO

Data Output Complement.

17

18

SDO

Data Output True.

18

19

VCCO

Positive power supply (Output Driver).

19

20

SD/HD

Data Rate Range Output. Output is high for SD and low for HD or 3G.

Serial Clock or Serial Data 2 Output select. Sets second output to output

20

21

SCO_EN

the clock when high and the data when low. This pin has an internal

pulldown.

—

10, 11, 23

VEE

Negative power supply.

—

22

RSVD

Reserved for future use. Do not connect.

DAP

DAP

VEE

Connect exposed DAP to negative power supply (ground).

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

4

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