50:

SDO, SCO/SDO2

VCC

VCC

50:

VCC

SDO, SCO/SDO2

SDI

VCC

VCC

SDI

2 k:

80 k:

1 pF

20 k:

VCC

2 k:

LMH0346

SNLS248J – APRIL 2007 – REVISED APRIL 2013

www.ti.com

Figure 3. Equivalent SDI Input Circuit (SDI, SDI)

Figure 4. Equivalent SDO Output Circuit (SDO, SDO, SCO/SDO2, SCO/SDO2)

OPERATING SERIAL DATA RATES

This device operates at serial data rates of 270 Mbps, 1483 Mbps, 1485 Mbps, 2967 Mbps, and 2970 Mbps. The

device does not lock to harmonics of these rates. The device does not lock and automatically enters the

reclocker bypass mode for the following data rates: 143 Mbps, 177 Mbps, 360 Mbps, and 540 Mbps.

SERIAL DATA CLOCK/SERIAL DATA 2 OUTPUT

The Serial Data Clock/Serial Data 2 Output is controlled by the SCO_EN input and provides either a second

retimed serial data output or a low jitter differential clock output appropriate to the serial data rate being

processed. When operating as a serial clock output, the rising edge of the clock will be positioned within the

corresponding serial data bit interval within 10% of the center of the data interval.

10

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