LMH0346

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SNLS248J – APRIL 2007 – REVISED APRIL 2013

AC ELECTRICAL CHARACTERISTICS

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.

(1)

Symbol

Parameter

Conditions

Reference

Min

Typ

Max

Units

BRSD

Serial Data Rate

SMPTE 259M, C

SDI, SDO

270

Mbps

BRSD

Serial Data Rate

SMPTE 292M

1483,

Mbps

1485

BRSD

Serial Data Rate

SMPTE 424M

2967,

Mbps

2970

TOLJIT

Serial Input Jitter

270 Mbps(2)(3)(4)

SDI

>6

UIP-P

Tolerance

TOLJIT

Serial Input Jitter

270 Mbps(2)(3)(5)

>0.6

UIP-P

Tolerance

TOLJIT

Serial Input Jitter

1483 or 1485 Mbps(2)(3)(4)

>6

UIP-P

Tolerance

TOLJIT

Serial Input Jitter

1483 or 1485 Mbps(2)(3)(5)

>0.6

UIP-P

Tolerance

TOLJIT

Serial Input Jitter

2967 or 2970 Mbps(2)(3)(4)

>6

UIP-P

Tolerance

TOLJIT

Serial Input Jitter

2967 or 2970 Mbps(2)(3)(5)

>0.6

UIP-P

Tolerance

tJIT

Serial Data Output Jitter

270 Mbps(3)(6)

SDO

0.01

0.03

UIP-P

tJIT

Serial Data Output Jitter

1483 or 1485 Mbps(3)(7)

0.03

0.04

UIP-P

tJIT

Serial Data Output Jitter

2967 or 2970 Mbps(3)(8)

0.06

0.08

UIP-P

BWLOOP

Loop Bandwidth

270 Mbps,

275

kHz

<0.1dB Peaking

1485 Mbps,

1.5

MHz

<0.1dB Peaking

2970 Mbps,

2.75

MHz

<0.1dB Peaking

FCO

Serial Clock Output

270 Mbps data rate

SCO

270

MHz

Frequency

FCO

Serial Clock Output

1483 Mbps data rate

1483

MHz

Frequency

FCO

Serial Clock Output

1485 Mbps data rate

1485

MHz

Frequency

FCO

Serial Clock Output

2967 Mbps data rate

2967

MHz

Frequency

FCO

Serial Clock Output

2970 Mbps data rate

2970

MHz

Frequency

tJIT

Serial Clock Output Jitter

2

3

psRMS

Serial Clock Output

See(3)

SDO, SCO

Alignment with respect to

40

60

%

Data Interval

Serial Clock Output Duty

See(3)

SCO

45

55

%

Cycle

TACQ

Acquisition Time

See(9)

15

ms

tr, tf

Input rise/fall time

10%–90%

Logic inputs

1.5

ns

(1)

Typical values are stated for: VCC = +3.3V, TA = +25°C.

(2)

Peak-to-peak amplitude with sinusoidal modulation per SMPTE RP 184-1996 paragraph 4.1. The test data signal shall be color bars.

(3)

This parameter is ensured by characterization over voltage and temperature limits.

(4)

Refer to “A1” in Figure 1 of SMPTE RP 184-1996.

(5)

Refer to “A2” in Figure 1 of SMPTE RP 184-1996.

(6)

PRBS 210

−1, input jitter = 31 psP-P

(7)

PRBS 210

−1, input jitter = 24 psP-P

(8)

PRBS 210

−1, input jitter = 22 psP-P

(9)

Measured from first SDI transition until Lock Detect (LD) output goes high (true).

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