Data Output

by

Transmitter

Data Output

by

Receiver

SCL

S

Start

Condition

Transmitter Stays Off the

Bus During the

Acknowledgement Clock

Acknowledgement

Signal From Receiver

1

2

3 - 6

7

8

9

LP3923

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SNVS567B – APRIL 2010 – REVISED MAY 2013

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter

releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver

must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the

high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to

receive the next byte.

Figure 10. Bus Acknowledge Cycle

”ACKNOWLEDGE AFTER EVERY BYTE” RULE

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge

signal after every byte received.

There is one exception to the “acknowledge after every byte” rule.

When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging

(“negative acknowledge”) the last byte clocked out of the slave. This “negative acknowledge” still includes the

acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

ADDRESSING TRANSFER FORMATS

Each device on the bus has a unique slave address. The LP3923 operates as a slave device with the address

7h’7E (binary nnnnnnnn). Before any data is transmitted, the master transmits the address of the slave being

addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address.

The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends

on the bit sent after the slave address — the eighth bit.

When the slave address is sent, each device in the system compares this slave address with its own. If there is a

match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the

R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.

CONTROL REGISTER WRITE CYCLE

•

Master device generates start condition.

•

Master device sends slave address (7 bits) and the data direction bit (r/w = '0').

•

Slave device sends acknowledge signal if the slave address is correct.

•

Master sends control register address (8 bits).

•

Slave sends acknowledge signal.

•

Master sends data byte to be written to the addressed register.

•

Slave sends acknowledge signal.

•

If master will send further data bytes the control register address will be incremented by one after

acknowledge signal.

•

Write cycle ends when the master creates stop condition.

CONTROL REGISTER READ CYCLE

•

Master device generates a start condition.

•

Master device sends slave address (7 bits) and the data direction bit (r/w = '0').

•

Slave device sends acknowledge signal if the slave address is correct.

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