Copyright © 2016, Texas Instruments Incorporated

IN

EN

PG

OUT

Overcurrent and Thermal

Protection

R1

Fast

Turnon

Circuit

Vreference

1.23 V

GND

R2

Low = OFF

High = ON

10

LP3988-Q1

SLAS928B – MARCH 2013 – REVISED NOVEMBER 2016

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Copyright © 2013–2016, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The LP3988-Q1 is a combination of a low-dropout linear regulator with an enable function, along with a Power

Good (PG) output. The enable function allows the LP3988-Q1 output to be selectively enabled, or disabled, as

needed. The PG output goes high when the LP3988-Q1 output voltage is typically above 95% of nominal.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Enable (En)

A high input on the EN pin (VEN ≥ VIH) activates the device, which turns the regulator to an ON state. A low input

on the EN pin (VEN ≤ VIL) disables the device which turns the regulator to an OFF state. Operating with VEN

between the VIL and the VIH thresholds is not recommended as the device status cannot be assured. For self-

bias applications where the VEN function is not needed, connect the EN pin to the IN pin.

8.3.2 Regulated Output (OUT)

The OUT pin is the regulated output voltage based on the internally pre-programmed voltage. The output has

current limitation. In the event that the regulator drops out of regulation due to low input voltage, the output tracks

the input minus a drop based on the load current. There is no UVLO circuitry. Device behavior is undefined when

VIN is below the minimum operating input voltage of either 2.5 V, or VOUT + 200 mV, whichever is greater.

8.3.3 Power Good (PG) Output

The PG pin is an open-drain output and can be pulled up to any 6 V, or lower rail through an external pullup

resistor. The PG pin is high-impedance when VOUT is greater than the PG trip high threshold (VTHH). If VOUT is

less than the PG trip low threshold (VTHL), the open-drain output turns on and pulls the PG output low. If output

voltage monitoring is not needed, the PG pin can be left floating or connected to GND. The behavior of the

Power-Good feature is not ensured when VIN is less than 2.5 V.

8.3.4 PG Delay Time

The Power-Good delay times (tON, tOFF) are defined as the time period from when VOUT crosses either the PG

high trip threshold voltage (VTHH), or the PG low trip threshold voltage (VTHL), to when the PG output changes to

the appropriate state. The power-good delay times are set internally, and both are typically 10 µs. There is no

external adjustment available to alter the delay times.