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LP3988-Q1

SLAS928B – MARCH 2013 – REVISED NOVEMBER 2016

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Copyright © 2013–2016, Texas Instruments Incorporated

9.2.2.6 Power Dissipation

Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is

critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and

load conditions and can be calculated with Equation 1.

PD(MAX) = (VIN(MAX) – VOUT) × IOUT(MAX)

(1)

Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available

voltage drop option that would still be greater than the dropout voltage (VDO). However, keep in mind that higher

voltage drops result in better dynamic (that is, PSRR and transient) performance.

On the SOT-23 (DBV) package, the primary conduction path for heat is through the device leads to the PCB,

predominately device lead 2 (GND). TI recommends that the trace from lead 2 be extended under the package

body and connected to an internal ground plane with thermal vias.

The maximum allowable junction temperature (TJ(MAX)) determines maximum power dissipation allowed (PD(MAX))

for the device package.

Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance

(RθJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to

Equation 2 or Equation 3:

TJ(MAX) = TA(MAX) + (RθJA × PD(MAX))

(2)

PD(MAX) = (TJ(MAX) – TA(MAX)) / RθJA

(3)

Unfortunately, this RθJA is highly dependent on the heat-spreading capability of the particular PCB design, and

therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded

in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copper-

spreading area, and is to be used only as a relative measure of package thermal performance.

9.2.2.7 Estimating Junction Temperature

The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction

temperatures of surface mount devices on a typical PCB board application. These characteristics are not true

thermal resistance values, but rather package specific thermal characteristics that offer practical and relative

means of estimating junction temperatures. These psi metrics are determined to be significantly independent of

copper-spreading area. The key thermal characteristics (ΨJT and ΨJB) are given in Thermal Information and are

used in accordance with Equation 4 or Equation 5.

TJ(MAX) = TTOP + (ΨJT × PD(MAX))

where

•

PD(MAX) is explained in Equation 1.

•

TTOP is the temperature measured at the center-top of the device package.

(4)

TJ(MAX) = TBOARD + (ΨJB × PD(MAX))

where

•

PD(MAX) is explained in Equation 1.

•

TBOARD is the PCB surface temperature measured 1-mm from the device package and centered on the

package edge.

(5)

For more information about the thermal characteristics ΨJT and ΨJB, see Semiconductor and IC Package Thermal

Metrics, available for download at www.ti.com.

For more information about measuring TTOP and TBOARD, see Using New Thermal Metrics, available for download

at www.ti.com.

For more information about the EIA/JEDEC JESD51 PCB used for validating RθJA, see the Thermal

Characteristics of Linear and Logic Packages Using JEDEC PCB Designs, available for download at www.ti.com.