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Output Limiters

Limiter Headroom (V)

0

0.5

2

1.5

1

2.5

100

75

50

25

0

−25

−50

−75

−100

Maximum Over Temperature

G046

Limiter Headroom = +VS − VH

= VL − (−VS)

Current = IVH or − IVL

Minimum

Over Temperature

OPA698M

SGLS287A – MAY 2005 – REVISED MARCH 2006

The output voltage is linearly dependent on the input(s) when it is between the limiter voltages VH (pin 8) and VL

(pin 5). When the output tries to exceed VH or VL, the corresponding limiter buffer takes control of the output

voltage and holds it at VH or VL. Because the limiters act on the output, their accuracy does not change with gain.

The transition from the linear region of operation to output limiting is sharp-the desired output signal can safely

come to within 30 mV of VH or VL with no onset of non-linearity. The limiter voltages can be set to within 0.7 V of

the supplies (VL≥– VS + 0.7 V, VH≤ +VS– 0.7 V). They must also be at least 400 mV apart (VH– VL≥ 0.4 V). When

pins 5 and 8 are left open, VH and VL go to the default voltage limit; the minimum values are given in the

electrical specifications. Looking at Figure 66 for the zero bias current case shows the expected range of (VS–

default limit voltages) = headroom.

Figure 66. Limiter Bias Current vs Bias Voltage

When the limiter voltages are more than 2.1 V from the supplies (VL≥– VS + 2.1 V or VH≤ +VS– 2.1 V), you can

use simple resistor dividers to set VH and VL (see Figure 47). Make sure to include the limiter input bias currents

(see Figure 54) in the calculations (that is, IVL = –50 µA out of pin 5 and IVH = +50 µA out of pin 8). For good

limiter voltage accuracy, run at least 1-mA quiescent bias current through these resistors. When the limiter

voltages need to be within 2.1 V of the supplies (VL≤– VS + 2.1 V or VH≥ +VS– 2.1 V), consider using low

impedance buffers to set VH and VL to minimize errors due to bias current uncertainty. This condition is typically

the case for single-supply operation (VS = +5 V). Figure 48 runs 2.5 mA through the resistive divider that sets VH

and VL. This limits errors due to IVH and IVL < ±1% of the target limit voltages. The limiters' dc accuracy depends

on attention to detail. The two dominant error sources can be improved as follows:

•

Power supplies, when used to drive resistive dividers that set VH and VL, can contribute large errors (for example, ±5%).

Using a more accurate source and bypassing pins 5 and 8 with good capacitors improves limiter PSRR.

•

The resistor tolerances in the resistive divider can also dominate. Use 1% resistors.

•

Other error sources also contribute, but should have little impact on the limiters' dc accuracy:

•

Reduce offsets caused by the limiter input bias currents. Select the resistors in the resistive divider(s) as described

above.

•

Consider the signal path dc errors as contributing to uncertainty in the usable output swing.

•

The limiter offset voltage only slightly degrades limiter accuracy. Figure 67 shows how the limiters affect distortion

performance. Virtually no degradation in linearity is observed for output voltage swinging right up to the limiter voltages.

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