www.ti.com

Power-On-Reset Functions

Reset

Reset Release

VCC

3.7 V

3 V

2.2 V

Internal Reset

System Clock

T0014-06

0 V

Don’t Care

3072 System Clocks

Audio Serial Interface

Audio Data Formats and Timing

PCM1780, PCM1781, PCM1782

SLES132B – MARCH 2005 – REVISED AUGUST 2006

The PCM1780/81/82 includes a power-on-reset function. Figure 21 shows the operation of this function. With the

system clock active and VCC > 3 V (typical, 2.2 V to 3.7 V), the power-on-reset function is enabled. The

initialization sequence requires 3072 system clocks from the time VCC > 3 V (typical, 2.2 V to 3.7 V). After the

initialization period, the PCM1780/82 is set to its reset default state, as described in the Mode Control Register

section of this data sheet.

During the reset period (3072 system clocks), the analog output is forced to the common voltage (VCOM), or

VCC/2. After the reset period, the internal register is initialized in the next 1/fS period and if SCK, BCK, and LRCK

are provided continuously, the PCM1780/81/82 provides the proper analog output with a group delay

corresponding to the input data.

Figure 21. Power-On-Reset Timing

The audio serial interface for the PCM1780/81/82 consists of a three-wire synchronous serial port. It includes

LRCK (pin 8), BCK (pin 7), and DATA (pin 6). BCK is the serial audio bit clock, and it is used to clock the serial

data present on DATA into the serial shift register of the audio interface. Serial data is clocked into the

PCM1780/81/82 on the rising edge of BCK. LRCK is the serial audio left/right word clock. It is used to latch

serial data into the internal registers of the serial audio interface.

Both LRCK and BCK should be synchronous with the system clock. Ideally, it is recommended that LRCK and

BCK be derived from the system clock input, SCK. LRCK is operated at the sampling frequency, fS. BCK can be

operated at 32, 48, or 64 times the sampling frequency.

Internal operation of the PCM1780/81/82 is synchronized with LRCK. Accordingly, internal operation of the

device is suspended when the sampling rate clock, LRCK, is changed or SCK and/or BCK is interrupted at least

for three bit-clock cycles. If SCK, BCK, and LRCK are provided continuously after this suspended condition, the

internal operation is resynchronized automatically within a period of less than 3/fS. External resetting is not

required.

The PCM1780/82 supports industry-standard audio data formats, including right-justified, I2S, and left-justified.

The PCM1781 supports I2S and 16-bit-word, right-justified. The data formats are shown in Figure 22. Data

formats are selected for the PCM1780/82 using the format bits, FMT[2:0], located in control register 20, and are

selected for the PCM1781 using the FMT pin. The default data format is 24-bit, left-justified. All formats require

binary 2s complement, MSB-first audio data. Figure 23 shows a detailed timing diagram for the serial audio

interface.

13

Submit Documentation Feedback