1/fS

32/fS

NORMAL DATA

ZERO DATA

UNDEFINED

DATA

NORMAL DATA

SYNCHRONOUS

ASYNCHRONOUS

SYNCHRONOUS

Resynchronization

Synchronization Lost

DOUT

State of Synchronization

T0020-05

16

PCM1803A

SLES142B – JUNE 2005 – REVISED JULY 2016

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Figure 23. ADC Digital Output for Loss of Synchronization and Resynchronization

7.4.3 Power Down

PDWN (pin 7) controls operation of the entire ADC. During power-down mode, supply current for the analog

portion is shut down and the digital portion is reset; also, DOUT (pin 12) is disabled. It is acceptable to halt the

system clock during power-down mode so that power dissipation is minimized. The minimum LOW pulse

duration on the PDWN pin is 100 ns.

TI recommends setting PWDN (pin 7) to LOW once to obtain stable analog performance when the sampling rate,

interface mode, data format, or oversampling control is changed.

Table 8. Power-Down Control

PWDN

POWER-DOWN MODE

LOW

Power-down mode

HIGH

Normal operation mode

7.4.4 HPF Bypass

The built-in function for DC-component rejection can be bypassed by BYPAS (pin 8) control. In bypass mode, the

DC component of the input analog signal, internal DC offset, and so forth, also are converted and included in the

digital output data.

Table 9. HPF Bypass Control

BYPAS

HPF (HIGH-PASS FILTER) MODE

LOW

Normal (no DC component in DOUT) mode

HIGH

Bypass (DC component in DOUT) mode

7.4.5 Oversampling Ratio Control

OSR (pin 16) controls the oversampling ratio of the delta-sigma modulator, ×64 or ×128. The ×128 mode is

available for fS ≤ 48 kHz.

Table 10. Oversampling Control

OSR

OVERSAMPLING RATIO

LOW

×64

HIGH

×128 (fS ≤ 48 kHz)