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PCM1803ADB Datasheet(PDF) 12 Page - Texas Instruments

Part # PCM1803ADB
Description  PCM1803A Single-Ended, Analog-Input 24-Bit, 96-kHz Stereo A/D Converter
PDF  30 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

PCM1803ADB Datasheet(HTML) 12 Page - Texas Instruments

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PCM1803A
SLES142B – JUNE 2005 – REVISED JULY 2016
www.ti.com
Product Folder Links: PCM1803A
Submit Documentation Feedback
Copyright © 2005–2016, Texas Instruments Incorporated
Table 2. System Clock Timing Requirements
PARAMETER
MIN
MAX
UNIT
tw(SCKH)
System clock pulse duration, HIGH
8
ns
tw(SCKL)
System clock pulse duration, LOW
8
ns
The quality of the system clock can influence the dynamic performance, because the PCM1803A operates based
on a system clock. Therefore, it may be required to consider the system-clock duty, jitter, and the time difference
between system-clock transition and BCK or LRCK transition in the slave mode.
7.4 Device Functional Modes
7.4.1 Serial Audio Data Interface
The PCM1803A interfaces the audio system through BCK (pin 11), LRCK (pin 10), and DOUT (pin 12).
7.4.1.1 Interface Mode
The PCM1803A supports master mode and slave mode as interface modes, and they are selected by MODE1
(pin 20) and MODE0 (pin 19) as shown in Table 3.
In master mode, the PCM1803A provides the timing of serial audio data communications between the
PCM1803A and the digital audio processor or external circuit. While in slave mode, the PCM1803A receives the
timing for data transfers from an external controller.
Table 3. Interface Mode
MODE1
MODE0
INTERFACE MODE
0
0
Slave mode (256 fS, 384 fS, 512 fS, 768 fS)
0
1
Master mode (512 fS)
1
0
Master mode (384 fS)
1
1
Master mode (256 fS)
7.4.1.1.1
Master Mode
In master mode, BCK and LRCK work as output pins, and these pins are controlled by timing, which is generated
in the clock circuit of the PCM1803A. The frequency of BCK is fixed at LRCK × 64. The 768-fS system clock is
not available in master mode.
7.4.1.1.2
Slave Mode
In slave mode, BCK and LRCK work as input pins. The PCM1803A accepts the 64-BCK/LRCK or 48-BCK/LRCK
format (only for 384 fS and 768 fS system clocks), not the 32-BCK/LRCK format.
7.4.1.2 Data Format
The PCM1803A supports four audio data formats in both master and slave modes, and the data formats are
selected by FMT1 (pin 18) and FMT0 (pin 17) as shown in Table 4. Figure 19 illustrates the data formats in slave
and master modes.
Table 4. Data Formats
FORMAT
FMT1
FMT0
DESCRIPTION
0
0
0
Left-justified, 24-bit
1
0
1
I2S, 24-bit
2
1
0
Right-justified, 24-bit
3
1
1
Right-justified, 20-bit



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