PCM4202

SBAS290B − JULY 2003 − SEPTEMBER 2004

www.ti.com

16

DSDBCK

DSDL

DSDR

D

N−3 DN−2 DN−1

D

N DN+1 DN+2 DN+3 DN+4

Figure 4. DSD Output Data Format

AUDIO SERIAL PORT OPERATION

This section provides additional details regarding the

PCM4202 audio serial port, utilized for 24-bit linear PCM

or 1-bit DSD output data. PCM output operation will be

described in this section, while DSD output mode

operation will be described in the following section.

For PCM data formats, the serial port is comprised of three

signals: BCK (pin 16), LRCK (pin 17), and DATA (pin 15).

The BCK signal functions as the data (or bit) clock for the

serial audio data. The LRCK is the left/right word clock for

the audio serial port. The LRCK and BCK clocks must be

synchronous. The DATA signal is the serial audio data

output, with data being clocked out on the falling edge of

the BCK signal. DATA carries audio data for both the Left

and Right channels.

As mentioned in the Audio Data Format section of this

datasheet, the audio serial port can operate in Master or

Slave mode. In Master mode, the BCK and LRCK clock

signals are outputs, derived from the system clock input,

SCKI. The BCK clock is fixed at 128fS for Single Rate

sampling mode, and at 64fS for Dual or Quad Rate

sampling modes. The LRCK clock operates at fS, the

output sampling rate (that is, 48kHz, 96kHz, etc.).

In Slave mode, the BCK and LRCK signals are inputs, with

the clocks being generated by a master timing source,

such as a DSP serial port, PLL clock synthesizer, or a

crystal oscillator/divider circuit. The BCK rate is typically

equal to 128fS in Single Rate sampling mode, and 64fS in

Dual or Quad Rate sampling modes. Although other BCK

clock rates are possible, they are not recommended as a

result if potential clock phase sensitivity issues, which can

degrade the dynamic performance of the PCM4202. The

LRCK clock must be operated at fS, the output sampling

rate.

Figure 5

illustrates

the

typical

audio

serial

port

connections between a PCM4202 and an audio signal

processor when using the PCM output data formats.

Figure 6 illustrates the audio serial port timing for both the

Master and Slave modes of operation.

LRCK

BCK

DATA

FSX

CLKR

DR

System Clock

PCM4202

DSP

SCKI

Figure 5. Typical Audio Serial Port Connections

for Left Justified, Right Justified, and I2S Data

Formats

LRCK

BCK

DATA

t

BCKDO

t

BCKP

t

BCKHL

t

LRCKHL

t

LRCKHL

t

LRCKHL

PARAMETE R

DESCRIP TIO N

MIN

MAX

UNITS

5

µs

2.25

µs

78

ns

35

ns

ns

10

LRCK Period

LRCK High/Low Time

BCK Period

BCK High/Low Time

SDOUT Data Output Delay from BCK Falling Edge

t

LRCKP

t

LRCKHL

t

BCKP

t

BCKHL

t

BCKDO

Figure 6. Master and Slave Mode Audio Serial Port Timing: Left Justified, Right Justified, and Philips I2S