AM53C96 datasheet(17/63 Pages) AMD

17 / 63 page

P R E L I M I N A R Y

AMD

Am53C94/Am53C96

Current Transfer Count Register

(00H–01H) Read Only

Current Transfer Count Register

CTCREG

Address: 00H–01H

Type: Read

CRVL15 CRVL14

CRVL13

CRVL12 CRVL11 CRVL10

CRVL9

CRVL8

xxx

xxxxx

76543

210

CRVL7

CRVL6

CRVL5

CRVL4

CRVL3

CRVL2

CRVL1

CRVL0

xxx

xxxxx

16506C-16

CTCREG – Bits 15:0 – CRVL 15:0 – Current

Value 15:0

This is a two-byte register. It counts down to keep track

of the number of DMA transfers. Reading this registers

will return the current value of the counter. The counter

will decrement by one for every byte transferred and two

for every word transferred over the SCSI bus. The trans-

action is complete when the count reaches zero. These

registers are automatically loaded with the values in the

Start Transfer Count Register every time a DMA com-

mand is issued.

In the target mode, this counter is decremented by the

active edge of

DACK during the Data-In phase and by

REQC during the Data-Out phase.

In the initiator mode, the counter is decremented by the

active edge of

DACK during the Synchronous Data-In

phase or by

ACKC during the Asynchronous Data-In

phase and by

DACK during the Data-Out phase.

Start Transfer Count Register (00H–01H)

Write Only

Start Transfer Count Register

STCREG

Address: 00H–01H

Type: Write

STVL15

STVL14

STVL13

STVL12

STVL11

STVL10

STVL9

STVL8

xxxxx

xxx

765

43210

STVL7

STVL6

STVL5

STVL4

STVL3

STVL2

STVL1

STVL0

xxx

xxxxx

16506C-017

STCREG – Bits 15:0 – STVL 15:0 – Start Value 15:0

This is a two-byte register. It contains the number of

bytes to be transferred during a DMA operation. The

value of this register is set to the number of bytes to be

transferred prior to a DMA transfer command. This reg-

ister retains its programmed value until it is overwritten

and is not affected by hardware or software reset.

Therefore, it is not necessary to reprogram the count for

subsequent DMA transfers of the same size. Writing a

zero to this register sets a maximum transfer count of

65536 bytes. The value in this register is undefined at

power-up.

FIFO Register (02H) Read/Write

FIFO Register

FFREG

Address: 02H

Type: Read/Write

76543

210

FF7

FF6

FF5

FF4

FF3

FF2

FF1

FF0

00000

000

16506C-18

FFREG – Bits 7:0 – FF 7:0 – FIFO 7:0

The bottom of the 16x9 FIFO is mapped into the FIFO

the bottom of the FIFO can be read or written. This is the

only register that can also be accessed by

DACK along

with

DMARD or DMAWR. This register is reset to zero

by hardware or software reset and also at the start of a

selection or reselection sequence.

Command Register (03H) Read/Write

Command Register

CMDREG

Address: 03H

Type: Read/Write

76543

210

DMA

CMD6

CMD5

CMD4

CMD3

CMD2

CMD1

CMD0

xxxxx

xxx

Command 6:0

Direct Memory

Access

16506C-019

Commands to the device are issued by writing to this

mand queuing. The second command can be issued be-

fore the first one is completed. The Reset command and

the Stop DMA command are not queued and are exe-

cuted immediately. Reading this register will return the

command currently being executed (or the last com-

mand executed if there are no pending commands).

AM53C96 Datasheet(PDF) 17 Page - Advanced Micro Devices

AM53C96 Datasheet(HTML) 17 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL