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S25FL128SDPMFIF Datasheet(PDF) 49 Page - Cypress Semiconductor |
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S25FL128SDPMFIF Datasheet(HTML) 49 Page - Cypress Semiconductor |
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49 / 149 page  Document Number: 001-98283 Rev. *M Page 48 of 148 S25FL128S/S25FL256S 7.5 Registers Registers are small groups of memory cells used to configure how the S25FL-S memory device operates or to report the status of device operations. The registers are accessed by specific commands. The commands (and hexadecimal instruction codes) used for each register are noted in each register description. The individual register bits may be volatile, non-volatile, or One Time Programmable (OTP). The type for each bit is noted in each register description. The default state shown for each bit refers to the state after power-on reset, hardware reset, or software reset if the bit is volatile. If the bit is non-volatile or OTP, the default state is the value of the bit when the device is shipped from Cypress. Non-volatile bits have the same cycling (erase and program) endurance as the main flash array. 7.5.1 Status Register 1 (SR1) Related Commands: Read Status Register (RDSR1 05h), Write Registers (WRR 01h), Write Enable (WREN 06h), Write Disable (WRDI 04h), Clear Status Register (CLSR 30h). Table 23. Register Descriptions Register Abbreviation Type Bit Location Status Register 1 SR1[7:0] Volatile 7:0 Configuration Register 1 CR1[7:0] Volatile 7:0 Status Register 2 SR2[7:0] RFU 7:0 AutoBoot Register ABRD[31:0] Non-volatile 31:0 Bank Address Register BRAC[7:0] Volatile 7:0 ECC Status Register ECCSR[7:0] Volatile 7:0 ASP Register ASPR[15:1] OTP 15:1 ASP Register ASPR[0] RFU 0 Password Register PASS[63:0] Non-volatile OTP 63:0 PPB Lock Register PPBL[7:1] Volatile 7:1 PPB Lock Register PPBL[0] Volatile Read Only 0 PPB Access Register PPBAR[7:0] Non-volatile 7:0 DYB Access Register DYBAR[7:0] Volatile 7:0 SPI DDR Data Learning Registers NVDLR[7:0] Non-volatile 7:0 SPI DDR Data Learning Registers VDLR[7:0] Volatile 7:0 Table 24. Status Register 1 (SR1) Bits Field Name Function Type Default State Description 7 SRWD Status Regis- ter Write Dis- able Non-Volatile 0 1 = Locks state of SRWD, BP, and configuration register bits when WP# is low by ignoring WRR command 0 = No protection, even when WP# is low 6 P_ERR Programming Error Occurred Volatile, Read only 0 1 = Error occurred. 0 = No Error 5 E_ERR Erase Error Occurred Volatile, Read only 0 1 = Error occurred 0 = No Error 4 BP2 Block Protec- tion Volatile if CR1[3]=1, Non-Volatile if CR1[3]=0 1 if CR1[3]=1, 0 when shipped from Cypress Protects selected range of sectors (Block) from Program or Erase 3 BP1 2 BP0 |
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