PL133-37

DS20006403A-page 4

 2020 Microchip Technology Inc.

2.0

PIN DESCRIPTION

The descriptions of the pins are listed in Table 2-1.

LAYOUT RECOMMENDATIONS

The following guidelines are to assist you with a performance-optimized PCB design.

Signal Integrity and Termination Considerations

• Keep traces short.

• Trace = Inductor. With a capacitive load, this

equals ringing.

• Long trace = Transmission line. Without proper

termination, this will cause reflections that look

like ringing.

• Design long traces as striplines or microstrips with

defined impedance.

• Match trace at one side to avoid reflections

bouncing back and forth.

Decoupling and Power Supply Considerations

• Place decoupling capacitors as close as possible

to the VDD pin to limit noise from the power

supply.

• Multiple VDD pins should be decoupled

separately for best performance.

• The addition of a ferrite bead in series with VDD

can help prevent noise from other board sources.

• The value of the decoupling capacitor is

frequency dependent. The typical value to use is

0.1 µF.

FIGURE 2-1:

Typical CMOS Termination.

TABLE 2-1:

PIN FUNCTION TABLE

Pin Number

Pin Name

Pin Type

Description

1

CLK1

O

Output clock (inverted).

2

GND

P

Ground connection.

3

FIN

I

Reference clock input.

4

CLK0

O

Output clock (inverted).

5

VDD

P

Power supply.

6

CLK2

O

Output clock (inverted).

Place Series Resistor as close as possible to CMOS output

CMOS Output Buffer

(Typical buffer impedance 20 )

To CMOS Input

Series Resistor

Use value to match output buffer impedance to

50 trace. Typical value 30

50 line