THS1206M datasheet(6/44 Pages) TI2

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THS1206

SLAS217H – MAY 1999 – REVISED JULY 2003#

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TIMING SPECIFICATION OF THE SINGLE CONVERSION MODE(1) (2)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Clock cycle of the internal clock oscillator

151

167

175

1 analog input

1.5

×tc

Pulse width CONVST

2 analog inputs

2.5

×tc

Pulse width, CONVST

3 analog inputs

3.5

×tc

4 analog inputs

4.5

×tc

tdA

Aperture time

1 analog input

×tc

Time between consecutive start of single con-

2 analog inputs

×tc

version

3 analog inputs

×tc

4 analog inputs

×tc

1 analog input,

TL = 1

6.5

×tc + 15

Delay time, DATA_AV becomes active for the

2 analog inputs, TL = 2

7.5

×tc +15

trigger level condition: TRIG0 = 0, TRIG1 = 0

3 analog inputs, TL = 3

8.5

×tc +15

4 analog inputs, TL = 4

9.5

×tc +15

1 analog input,

TL = 4

×t2 +6.5×tc+15

td(DATA AV)

Delay time, DATA_AV becomes active for the

2 analog inputs, TL = 4

t2 +7.5×tc+15

td(DATA_AV)

trigger level condition: TRIG0 = 1, TRIG1 = 0

3 analog inputs, TL = 6

t2 +8.5×tc+15

4 analog inputs, TL = 8

t2 +9.5×tc+15

1 analog input,

TL = 8

×t2 +6.5×tc+15

Delay time, DATA_AV becomes active for the

2 analog inputs, TL = 8

×t2 +7.5×tc+15

trigger level condition: TRIG0 = 0, TRIG1 = 1

3 analog inputs, TL = 9

×t2 +8.5×tc+15

4 analog inputs, TL = 12

×t2 +9.5×tc+15

D l

DATA AV b

1 analog input,

TL = 14

×t2 +6.5×tc+15

td(DATA_AV)

Delay time, DATA_AV becomes active for the

trigger level condition: TRIG0 = 1 TRIG1 = 1

2 analog inputs, TL = 12

×t2 +7.5×tc+15

(

)

trigger level condition: TRIG0 = 1, TRIG1 = 1

3 analog inputs, TL = 12

×t2 +8.5×tc+15

(1) Timing parameters are ensured by design but are not tested.

(2) See Figure 24.

PIN ASSIGNMENTS

BVDD

BGND

D10/RA0

D11/RA1

CONV_CLK (CONVST)

DATA_AV

AINP

AINM

BINP

BINM

REFIN

REFOUT

REFP

REFM

AGND

AVDD

CS0

CS1

WR (R/W)

DVDD

DGND

DA PACKAGE

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