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PIC16F570 Datasheet(PDF) 12 Page - Microchip Technology

Part # PIC16F570
Description  20-Pin, 8-Bit Flash Microcontroller
PDF  134 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16F570 Datasheet(HTML) 12 Page - Microchip Technology

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PIC16F527
DS40001652C-page 12
 2012-2014 Microchip Technology Inc.
4.0
MEMORY ORGANIZATION
The PIC16F527 memories are organized into program
memory and data memory (SRAM).The self-writable
portion of the program memory called self-writable
Flash data memory is located at addresses 400h-43Fh.
All program mode commands that work on the normal
Flash memory, work on the Flash data memory. This
includes bulk erase, row/column/cycling toggles, Load
and Read data commands (Refer to Section 5.0 “Self-
Writable Flash Data Memory Control” for more
details). For devices with more than 512 bytes of
program memory, a paging scheme is used. Program
memory pages are accessed using one STATUS
register bit. For the PIC16F527, with data memory
register files of more than 32 registers, a banking
scheme is used. Data memory banks are accessed
using the File Select Register (FSR).
4.1
Program Memory Organization for
PIC16F527
The PIC16F527 device has an 11-bit Program Counter
(PC) capable of addressing a 2K x 12 program memory
space. Program memory is partitioned into user memory,
data memory and configuration memory spaces.
The user memory space is the on-chip user program
memory. As shown in Figure 4-1, it extends from 0x000
to 0x3FF and partitions into pages, including an
Interrupt vector at address 0x004 and a Reset vector at
address 0x3FF.
The data memory space is the self-writable Flash data
memory block and is located at addresses PC = 400h-
43Fh. All program mode commands that work on the
normal Flash memory, work on the Flash data memory
block. This includes bulk erase, Load and Read data
commands.
The configuration memory space extends from 0x440
to 0x7FF. Locations from 0x448 through 0x49F are
reserved. The user ID locations extend from 0x440
through 0x443. The Backup OSCCAL locations extend
from 0x444 through 0x447. The Configuration Word is
physically located at 0x7FF.
Refer
to
“PIC16F527
Memory
Programming
Specification” (DS41640) for more details.
FIGURE 4-1:
MEMORY MAP
005h
1FFh
Reset Vector
On-chip User
Program
Memory (Page 0)
200h
3FFh
3FEh
User ID Locations
Reserved
Configuration Word
400h
443h
444h
7FEh
7FFh
43Fh
440h
Unimplemented
On-chip User
Program
Memory (Page 1)
Self-writable
448h
49Fh
Backup OSCCAL
Locations
447h
4A0h
Flash Data Memory
Interrupt Vector
000h
004h



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