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TLC59482RGET Datasheet(PDF) 21 Page - Texas Instruments |
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TLC59482RGET Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 35 page ![]() GS1 0B When Auto data refresh mode is enabled, the all data in GS second data latch are copied to GS third data latch at 65536th GSCLK. GS15 14C GS15 15C GS0 1B GS0 15B Dotted line LAT timing is accepted. OUT15 GS1 0B SIN LAT GS0 15B SCLK 1 GS0 5B GS0 4B GS0 3B Shift Register LSB Data (Internal) GS1 1B GS1 0B Shift Register LSB+1 Data (Internal) GS1 14B GS1 13B Shift Register MSB-1 Data (Internal) GS1 15B GS1 14B OUT1 SOUT GS Second Data GS Third Data GS15 13C GS0 2B GS0 0B GS0 3B 12 13 14 15 16 GS0 0B GS0 4B GS1 0B New 16-bit GS Data OUT0 Old 16-bit GS Data Old 256-bit GS Data New 256-bit GS Data Old 256-bit GS Data New 256-bit GS Data The all data in 16-bit common shift register are copied to GS0 first data latch at falling edge of LAT. 2 or 3 rising edge of SCLK is needed to be input while LAT is high level. OUT0 GSCLK - - - - 65535 1 3 65534 65536 2 - - - - GS15 12C GS15 11C GS15 10C GS0 12B GS0 14B GS0 13B GS0 11B GS0 10B GS0 9B GS0 11B GS0 13B GS0 12B GS0 10B GS0 9B GS0 8B GS15 14C GS0 0B GS15 15C GS15 13C GS15 12C GS15 11C GS15 13C GS15 15C GS15 14C GS15 12C GS15 11C GS15 10C OFF ON The all data in GS first data latch are copied to GS second data latch. GS0 2B GS0 1B GS0 6B GS0 5B GS0 4B GS0 1B GS0 3B GS0 2B GS1 3B GS1 2B GS1 1B GS0 14B GS1 0B GS0 15B GS1 4B GS1 3B GS1 2B GS0 15B GS1 1B GS Data Latch Address Counter (Internal) OUT15 GS First Data Latch (Internal) OUT0 GS First Data Latch Latch (Internal) OUT (GS data = FFFFh) Dotted line LAT timing is accepted. Latch (Internal) (Internal) The LATGS command executes. TLC59482 www.ti.com SBVS218 – DECEMBER 2012 Figure 20. Auto Data Refresh Function (XRFRESH = 0, LATMODE = 0) Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: TLC59482 |
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