16-bit

Common

Shift Register

223

32

LOAD

GS

First Latch

for OUT0

SOUT

256

LSB

MSB

0

15

LSB

MSB

0

255

SIN

LSB

0

LSB

255

MSB

15 16

31

240

239

224

223

16

16

16

16

16

16

16

16

0

MSB

15

32

15 16

31

240

239

224

Function Control (FC) Data Latch

LSB

0

255

MSB

16

32

15 16

31

240

239

224

223

16

16

16

16

GS

First Latch

for OUT1

GS

First Latch

for OU14

GS

First Latch

for OUT15

GS

Second Latch

for OUT0

GS

Second Latch

for OUT1

GS

Second Latch

for OUT14

GS

Second Latch

for OUT15

GS

Third Latch

for OUT0

GS

Third Latch

for OUT1

GS

Third Latch

for OUT14

GS

Third Latch

for OUT15

SCLK

LAT

DIN

Latch Signal for GS Second

Data Latch (Internal)

To Constant Current Output/

PWM Timing Control/Data Latch

Control Circuit

To PWM Timing

Control Circuit

OUT15 GS Data Latch (Internal)

OUT14 GS Data Latch (Internal)

OUT13~2 GS Data Latch (Internal)

OUT1 GS Data Latch (Internal)

OUT0 GS Data Latch (Internal)

16

16

12

Latch Signal for GS Third

Data Latch (Internal)

Latch Signal for FC

Data Latch (Internal)

16

16

TLC59482

SBVS218 – DECEMBER 2012

www.ti.com

REGISTER AND DATA LATCH CONFIGURATION

The TLC59482 has one common shift register, one function control (FC) data latch, and a set of three data

latches: the first, second, and third grayscale (GS) data latches. The common shift register and FC data latch are

16 bits long and the GS data latches are 256 bits long. Figure 21 shows the common shift register and the data

latches configuration.

Figure 21. Shift Register and Data Latch Configuration

22

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