The all data in 16-bit common shift

register are copied to GS1 first data

latch at 1’st “WRTGS” command

GS15

14A

GS0

0

GS0

0A

OUT14

GS13

15A

GS0

3A

GS1

1A

GS15

15A

Dotted line LAT timing is also accepted.

GS14

15A

GS15

0A

GS0

14

SIN

LAT

GS15

15A

GS15

1A

SCLK

GS0

15

GS0

1

GS Data Latch

Address Counter

(Internal)

SOUT

GS Second

Data Latch

(Internal)

GS Third

Data Latch

(Internal)

257

269

270

271

272

253

254

255

256

GS15

1A

GS15

0A

OUT15 GS First

Data Latch

(Internal)

OUT15

Old 256-bitGS Data

New 256-Bit

GS Data

All data in the

GS data latch are copied

first

to both the second and

third

data latches

GS

when the auto data refresh mode is disabled.

.

The all data in GS first data latch

are copied to GS second data latch.

GS0

0

GS14

0A

GS14

1A

GS0

0A

GS0

1A

GS14

15A

GS1

0A

GS1

14A

GS0

2A

GS1

14A

1

15

16

17

31

32

GS0

15A

GS0

1A

OUT13

OUT15

OUT15 GS First

Data Latch

(Internal)

New 16-Bit GS Data

OUT0 GS First

Data Latch

(Internal)

Old

GS Data

16-Bit

Old 16-bit GS Data

New 16-Bit GS Data

New

GS Data

16-Bit

Old

GS Data

16-Bit

The counter is set to OUT15 when

the

command is input.

LATGS

The counter is decreased when

the WRTGS command is input.

All data in the16-bit common shift

register are copied to the

GS0 data

first

latch at the 16th WRTGS command.

All data in the 16-bit common shift

register are copied to the

GS1 data

first

latch at the 2nd WRTGS command.

OUT15

OUT14

OUT0

OUT15

LATMODE Bit

in FC Data Latch

(Internal)

1

16-Bit Common

Shift Register

(Internal)

1st WRTGS

Command

2nd WRTGS

Command

16th WRTGS

Command

LATGS

Command

GS0

2A

GS0

3A

1

(1)

1

1

1

1

Old 256-Bit GS Data

TLC59482

www.ti.com

SBVS218 – DECEMBER 2012

Figure 28. 256-Bit GS Data Write Sequence Timing Diagram

(16 × WRTGS + 1 LATGS, LATMODE = 1)

NOISE REDUCTION

Large surge currents may flow through the device and the board on which the device is mounted if all 16 outputs

turn on or off simultaneously. These large current surges can introduce detrimental noise and electromagnetic

interference (EMI) into other circuits.

The TLC59482 turns the outputs on with a series delay for each group independently to provide a soft-start

feature. The output current sinks are grouped into four groups. The first output group that is turned on/off are

OUT0, OUT7, OUT8, and OUT15; the second output group is OUT1, OUT6, OUT9, and OUT14; the third output

group is OUT2, OUT5, OUT10, and OUT13; and the fourth output group is OUT3, OUT4, OUT11, and OUT12.

Each output group is turned on and off sequentially with a 5-ns (typical) delay between the groups. However,

each output on/off is controlled by the GS clock.

Copyright © 2012, Texas Instruments Incorporated

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