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W39V080AP Datasheet(PDF) 4 Page - Winbond

Part # W39V080AP
Description  1M 횞 8 CMOS FLASH MEMORY WITH LPC INTERFACE
PDF  34 Pages
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W39V080AP Datasheet(HTML) 4 Page - Winbond

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W39V080A
- 4 -
3.
PIN CONFIGURATIONS
4.
BLOCK DIAGRAM
#WE(#LFRAME)
DQ4(RSV)
DQ3(LAD3)
DQ7(U/#L)
DQ6(D/#F)
#OE(#INIT)
DQ5(RSV)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
32L STSOP
24
23
22
21
20
19
18
17
A3(ID3)
MODE
R/#C(CLK)
NC
VDD
A10(GPI4)
Vpp
A9(GPI3)
A8(GPI2)
#RESET
A7(GPI1)
A6(GPI0)
A2(ID2)
A1(ID1)
A0(ID0)
DQ2(LAD2)
DQ1(LAD1)
DQ0(LAD0)
A5(#WP)
A4(#TBL)
V SS
VSS
RY/#BY(RSV)
NC
NC
A
1
0
^
G
P
I
4
v
5
6
7
9
10
11
12
13
29
28
27
26
25
24
23
22
21
30
31
32
1
2
3
4
8
20
19
18
17
16
15
14
D
Q
1
^
L
A
D
1
v
V
S
S
D
Q
6
^
D
/
#
v
#
R
E
S
E
T
V
D
D
R
/
#
C
^
C
L
K
v
A
9
^
G
P
I
3
v
32L PLCC
DQ0(LAD0)
A7(GPI1)
A6(GPI0)
A4(#TBL)
A3(ID3)
A2(ID2)
A1(ID1)
A0(ID0)
A5(#WP)
MODE
DQ7(U/#L)
#WE(#LFRAME)
#OE(#INIT)
NC
A
8
^
G
P
I
2
v
D
Q
2
^
L
A
D
2
v
D
Q
3
^
L
A
D
3
v
D
Q
4
^
R
S
V
v
D
Q
5
^
R
S
V
v
VSS
RY/#BY(RSV)
VDD
NC
V
P
P
F
#WE(#LFRAME)
DQ3(LAD3)
DQ2(LAD2)
DQ1(LAD1)
DQ0(LAD0)
1
40L TSOP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vpp
VDD
CLK
A9(GPI3)
A8(GPI2)
NC
VSS
VSS
VDD
DQ7(U/#L)
DQ6(D/#F)
VDD
VSS
NC
MODE
A4(#TBL)
A5(#WP)
2
3
4
5
6
7
24
21
22
23
NC
NC
NC
A10(GPI4)
NC
#RESET
NC
NC
A7(GPI1)
A6(GPI0)
DQ5(RSV)
DQ4(RSV)
A0(ID0)
A1(ID1)
A2(ID2)
A3(ID3)
RY/#BY(RSV)
#OE(#INIT)
9
10
11
12
13
14
15
16
8
17
18
19
20
0FFFFF
LAD[3:0]
Program-
mer
Interface
000000
020000
01FFFF
010000
00FFFF
#RESET
MODE
A[10:0]
DQ[7:0]
#OE
#WE
R/#C
LPC
Interface
CLK
#LFRAME
0F0000
0EFFFF
64K BYTES BLOCK 0
030000
02FFFF
#INIT
#WP
#TBL
0E0000
0DFFFF
0D0000
0CFFFF
64K BYTES BLOCK 1
64K BYTES BLOCK 2
64K BYTES BLOCK 13
64K BYTES BLOCK 14
64K BYTES BLOCK 15
RY/#BY
5.
PIN DESCRIPTION
INTERFACE
SYM.
PGM
LPC
PIN NAME
MODE
*
*
Interface Mode Selection
#RESET
*
*
Reset
#INIT
*
Initialize
#TBL
*
Top Boot Block Lock
#WP
*
Write Protect
CLK
*
CLK Input
GPI[4:0]
*
General Purpose Inputs
ID[3:0]
*
Identification Inputs
Pull Down with Internal Resistors
LAD[3:0]
*
Address/Data Inputs
#LFRAME
*
LPC Cycle Initial
D/#F
*
Dual Bios/Full Chip
Pull Down with Internal Resistors
U/#L
*
Upper 4M/Lower 4M
Pull Down with Internal Resistors
R/#C
*
Row/Column Select
A[10:0]
*
Address Inputs
DQ[7:0]
*
Data Inputs/Outputs
#OE
*
Output Enable
#WE
*
Write Enable
RY/#BY
*
Ready/Busy
VDD
*
*
Power Supply
VSS
*
*
Ground
RSV
*
*
Reserve Pins
NC
*
*
No Connection



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