W39V080AP datasheet(28/34 Pages) WINBOND

28 / 34 page

W39V080A

- 28 -

Timing Waveforms for LPC Interface Mode, continued

14.5 Toggle Bit Timing Diagram

Read the DQ6 to see if the internal write complete or not.

LAD[3:0]

Start

Memory

Read

Cycle

Load Address in 8 Clocks

CLK

1 Clock

TAR

Next Start

1 Clock

2 Clocks

1 Clock

010Xb

0000b

XXXXb

Address

Sync

TAR

1111b

Tri-State

0000b

Data out 2 Clocks

X,D6,XXb

Data

XXXXb

0000b

LAD[3:0]

Start

Memory

Read

Cycle

Load Address in 8 Clocks

CLK

1 Clock

TAR

Next Start

1 Clock

2 Clocks

1 Clock

010Xb

0000b

XXXXb

Address

Sync

TAR

1111b

Tri-State

0000b

Data out 2 Clocks

Data

0000b

When internal write complete, the DQ6 will stop toggle.

X,D6,XXb

XXXXb

LAD[3:0]

1st Start

Load Address "An" in 8 Clocks

CLK

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

An[15:12]

Load Data "Dn"

in 2 Clocks

Dn[7:4]

Write the last command(program or erase) to the device in LPC mode.

Address

Sync

TAR

Data

1111b

Tri-State

0000b

An[11:8]

An[7:4]

An[3:0]

Dn[3:0]

An[19:16]

Memory

Write

Cycle

XXXXb

1 Clock

#LFRAME

#RESET

#LFRAME

#RESET

#LFRAME

#RESET

W39V080AP Datasheet(PDF) 28 Page - Winbond

W39V080AP Datasheet(HTML) 28 Page - Winbond

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Datasheet Download

Link URL