REFERENCE CIRCUIT DESIGN

CLOCKING

REF

T

REF

B

I

SET

0.1

µF

2.2

µF

2

Ω

56.2k

Ω

2

Ω

2.2

µF

0.1

µF

ADS5270

ADS5270

www.ti.com............................................................................................................................................... SBAS293F – JANUARY 2004 – REVISED JANUARY 2009

The device also supports the use of external

reference voltages. This mode involves forcing REFT

The digital beam-forming algorithm relies on gain

and REFB externally. In this mode, the internal

matching across all receiver channels. A typical

reference buffer is tri-stated. Since the switching

system would have about 12 octal ADCs on the

current

for

the

eight

ADCs

come

from

the

board. In such a case, it is critical to ensure that the

externally-forced references, it is possible for the

gain is matched, essentially requiring the reference

performance to be slightly less than when the internal

voltages seen by all the ADCs to be the same.

references are used. It should be noted that in this

Matching references within the eight channels of a

mode, VCM and ISET continue to be generated from

chip is done by using a single internal reference

the internal bandgap voltage, as in the internal

voltage buffer. Trimming the reference voltages on

reference mode. It is therefore important to ensure

each chip during production ensures the reference

that

the

common-mode

voltage

of

the

voltages are well-matched across different chips.

externally-forced

reference

voltages

matches

to

within 50mV of VCM. The state of the reference

All bias currents required for the internal operation of

voltages during various combinations of PD and

the device are set using an external resistor to

INT/EXT is shown in Table 1.

ground at pin ISET. Using a 56kΩ resistor on ISET

generates an internal reference current of 20A. This

Table 1. State of Reference Voltages for Various

current is mirrored internally to generate the bias

Combinations of PD and INT/EXT

current for the internal blocks. Using a larger external

resistor at ISET reduces the reference bias current and

PD

0

0

1

1

thereby scales down the device operating power.

INT/EXT

0

1

0

1

However, it is recommended that the external resistor

REFT

Tri-State

1.95V

Tri-State

Tri-State

be within 10% of the specified value of 56k

Ω so that

REFB

Tri-State

0.95V

Tri-State

Tri-State

the internal bias margins for the various blocks are

proper.

VCM

1.45V

1.45V

Tri-State(1)

Tri-State(1)

Buffering the internal bandgap voltage also generates

a voltage called VCM, which is set to the midlevel of

REFT and REFB, and is accessible on a pin. It is

The eight channels on the chip operate from a single

meant as a reference voltage to derive the input

ADCLK input. To ensure that the aperture delay and

common-mode in case the input is directly coupled. It

jitter are same for all the channels, a clock tree

can

also

be

used

to

derive

the

reference

network is used to generate individual sampling

common-mode voltage in the external reference

clocks to each channel. The clock paths for all the

mode.

channels are matched from the source point all the

way to the sample-and-hold amplifier. This ensures

When using the internal reference mode, a 2

Ω

that the performance and timing for all the channels

resistor should be added between the reference pins

are identical. The use of the clock tree for matching

(REFT and REFB) and the decoupling capacitor, as

introduces an aperture delay, which is defined as the

shown in Figure 17. If the device is used in the

delay between the rising edge of ADCLK and the

external reference mode, this 2

Ω resistor is not

actual instant of sampling. The aperture delays for all

required.

the channels are matched to the best possible extent.

However, a mismatch of ±20ps (±3

σ) could exist

between the aperture instants of the eight ADCs

within the same chip. However, the aperture delays of

ADCs across two different chips can be several

hundred

picoseconds

apart.

Another

critical

specification is the aperture jitter that is defined as

the uncertainty of the sampling instant. The gates in

the clock path are designed to provide an rms jitter of

approximately 1ps.

Ideally, the input ADCLK should have a 50% duty

cycle. However, while routing ADCLK to different

components onboard, the duty cycle of the ADCLK

reaching the ADS5270 could deviate from 50%. A

smaller (or larger) duty cycle reduces the time

available for sample or hold phases of each circuit,

and is therefore not optimal. For this reason, the

Figure 17. Internal Reference Mode

internal PLL is used to generate an internal clock that

has 50% duty cycle. The input sampling instant,

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