ADS5270

SBAS293F – JANUARY 2004 – REVISED JANUARY 2009............................................................................................................................................... www.ti.com

PIN DESCRIPTIONS

NAME

PIN #

I/O

DESCRIPTION

ADCLK

71

I

Data Converter Clock Input

ADCLKN

42

O

Negative LVDS ADC Clock Output

ADCLKP

41

O

Positive LVDS ADC Clock Output

AVDD

1, 7, 14, 47, 54, 60, 63, 70, 75

I

Analog Power Supply

AVSS

4, 8, 11, 50, 53, 57, 61, 62, 68, 72–74, 79, 80

I

Analog Ground

CS

76

I

Chip Select; 0 = Select, 1 = No Select

IN1N

3

I

Channel 1 Differential Analog Input Low

IN1P

2

I

Channel 1 Differential Analog Input High

IN2N

6

I

Channel 2 Differential Analog Input Low

IN2P

5

I

Channel 2 Differential Analog Input High

IN3N

10

I

Channel 3 Differential Analog Input Low

IN3P

9

I

Channel 3 Differential Analog Input High

IN4N

13

I

Channel 4 Differential Analog Input Low

IN4P

12

I

Channel 4 Differential Analog Input High

IN5N

49

I

Channel 5 Differential Analog Input Low

IN5P

48

I

Channel 5 Differential Analog Input High

IN6N

52

I

Channel 6 Differential Analog Input Low

IN6P

51

I

Channel 6 Differential Analog Input High

IN7N

56

I

Channel 7 Differential Analog Input Low

IN7P

55

I

Channel 7 Differential Analog Input High

IN8N

59

I

Channel 8 Differential Analog Input Low

IN8P

58

I

Channel 8 Differential Analog Input High

INT/EXT

69

I

Internal/External Reference Select; 0 = External, 1 = Internal. Weak pull-up to supply.

ISET

64

I/O

Bias Current Setting Resistor of 56.2k

Ω to Ground

LCLKN

20

O

Negative LVDS Clock

LCLKP

19

O

Positive LVDS Clock

LVDD

25, 35

I

LVDS Power Supply

LVSS

15, 17, 18, 26, 36, 43, 44, 46

I

LVDS Ground

OUT1N

22

O

Channel 1 Negative LVDS Data Output

OUT1P

21

O

Channel 1 Positive LVDS Data Output

OUT2N

24

O

Channel 2 Negative LVDS Data Output

OUT2P

23

O

Channel 2 Positive LVDS Data Output

OUT3N

28

O

Channel 3 Negative LVDS Data Output

OUT3P

27

O

Channel 3 Positive LVDS Data Output

OUT4N

30

O

Channel 4 Negative LVDS Data Output

OUT4P

29

O

Channel 4 Positive LVDS Data Output

OUT5N

32

O

Channel 5 Negative LVDS Data Output

OUT5P

31

O

Channel 5 Positive LVDS Data Output

OUT6N

34

O

Channel 6 Negative LVDS Data Output

OUT6P

33

O

Channel 6 Positive LVDS Data Output

OUT7N

38

O

Channel 7 Negative LVDS Data Output

OUT7P

37

O

Channel 7 Positive LVDS Data Output

OUT8N

40

O

Channel 8 Negative LVDS Data Output

OUT8P

39

O

Channel 8 Positive LVDS Data Output

PD

16

I

Power-Down; 0 = Normal, 1 = Power-Down

REFB

66

I/O

Reference Bottom Voltage (2

Ω resistor in series with a 0.1F capacitor to ground)

REFT

67

I/O

Reference Top Voltage (2

Ω resistor in series with a 0.1F capacitor to ground)

RESET

45

I

Reset to Default; 0 = Reset, 1 = Normal. Weak pull-down to ground.

SCLK

78

I

Serial Data Clock

SDATA

77

I

Serial Data Input

VCM

65

O

Common-Mode Output Voltage

12

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