LVDS BUFFERS

NOISE COUPLING ISSUES

External

Termination

Resistor

OUT

P

High

Low

OUT

N

Low

High

ADS5270

SBAS293F – JANUARY 2004 – REVISED JANUARY 2009............................................................................................................................................... www.ti.com

however, is determined by the rising edge of the

with a register programmability that allows it to revert

external clock and is not affected by jitter in the PLL.

to MSB first. The serializer also gives out a 1x clock

In addition to generating a 50% duty cycle clock for

and

a

6x

clock.

The

6x

clock

(denoted

as

the ADC, the PLL also generates a 12x clock that is

LCLKP/LCLKN) is meant to synchronize the capture of

used by the serializer to convert the parallel data from

the LVDS data.

the ADC to a serial stream of bits.

Deskew mode can be enabled as well, using a

The use of the PLL automatically dictates the

register setting. This mode gives out a data stream of

minimum sample rate to be about 20MSPS. The PLL

alternate 0s and 1s and can be used to determine the

also requires the input clock to be free-running. If the

relative delay between the 6x clock and the output

input clock is momentarily stopped (for a duration of

data for optimum capture. A 1x clock is also

less than 300ns) then the PLL would require

generated by the serializer and transmitted through

approximately 10

µs to lock back to the input clock

the LVDS buffer. The 1x clock (referred to as

frequency.

ADCLKP/ADCLKN) is used to determine the start of

the 12-bit data frame. Sync mode (enabled through a

register setting) gives out a data of six 0s followed by

six 1s. Using this mode, the 1x clock can be used to

The LVDS buffer has two current sources, as shown

determine the start of the data frame. In addition to

in Figure 18. OUTP and OUTN are loaded externally

the deskew mode pattern and the sync mode pattern,

by a resistive load that is ideally about 100

Ω.

a custom pattern can be defined by the user and

Depending on whether the data is 0 or 1, the currents

output from the LVDS buffer. The LVDS buffers are

are directed in one direction or the other through the

tri-stated in the power-down mode. The LVDS outputs

resistor. The LVDS buffer has four current settings.

are weakly forced to 1.2V through 10k

Ω resistors

The default current setting is 3.5mA, and provides a

(from each output pin to 1.2V).

differential drop of about ±350mV across the 100

Ω

resistor.

The single-ended output impedance of the LVDS

High-speed mixed signals are sensitive to various

drivers is very high because they are current-source

types of noise coupling. One of the main sources of

driven. If there are excessive reflections from the

noise is the switching noise from the serializer and

receiver, it might be necessary to place a 100

Ω

the output buffers. Maximum care is taken to isolate

termination resistor across the outputs of the LVDS

these noise sources from the sensitive analog blocks.

drivers to minimize the effect of reflections. In such a

As a starting point, the analog and digital domains of

situation, the output current of the LVDS drivers can

the chip are clearly demarcated. AVDD and AVSS

be increased to regain the output swing.

are used to denote the supplies for the analog

sections, while LVDD and LVSS are used to denote

the digital supplies. Care is taken to ensure that there

is minimal interaction between the supply sets within

the

device.

The

extent

of

noise

coupled

and

transmitted from the digital to the analog sections

depends on the following:

1. The

effective

inductances

of

each

of

the

supply/ground sets.

2. The isolation between the digital and analog

supply/ground sets.

Smaller effective inductance of the supply/ground

pins leads to better suppression of the noise. For this

reason,

multiple

pins

are

used

to

drive

each

supply/ground. It is also critical to ensure that the

impedances of the supply and ground lines on board

are kept to the minimum possible values. Use of

ground planes in the board as well as large

decoupling

capacitors

between

the

supply

and

Figure 18. LVDS Buffer

ground lines are necessary to get the best possible

SNR from the device.

The LVDS buffer gets data from a serializer that

takes the output data from each channel and

serializes it into a single data stream. For a clock

frequency of 40MHz, the data rate output of the

serializer is 480Mbps. The data comes out LSB first,

20

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