Converter Timing

f

=

MIN

=39.2kHz

P

L1

OUT

MAX

´

=

h

(V

)

´

IN_MIN

2

V

Ö

IN_MIN

´ 2

V

OUT

1 -

300W

390

H

m

´

0.92

(85V)

´

2

85V

Ö

´ 2

390V

1 -

(36)

R

=

TSET

»

W

121k

4.85V

4

s

f

m

´

´

MIN

=

133kW

V

Ö

IN_MIN

´ 2

V

OUT

1 -

4.85V

4

s

39.2kHz

m

´

´

133kW

85V

Ö

´ 2

390V

1 -

(37)

f

=

MAX

» 550kHz

2

s

R

m ´

T

=

133kW

2

s

121k

m

W

´

133kW

(38)

Programming VOUT

R =3MW

C

(39)

V

=6V

REF

(40)

R =

D

»

W

47k

(V

V

)

-

OUT

REF

=

V

R

REF

C

´

(390V

6V)

-

6V

3M

´

W

(41)

V

=6.45V

OVP

=418V

R

D

=6.45V

R +R

C

D

47kW

3M

+47k

W

W

(42)

Loop Compensation

g

=96

S

m

m

(43)

H=

» 0.015

=

V

REF

V

OUT

6V

390V

(44)

R =

Z

=6.313k

6.34k

»

W

W

=

100mV

V

H

g

RIPPLE

m

´

´

100mV

11V

0.015

96

S

m

´

´

(45)

UCC28060

www.ti.com .................................................................................................................................................... SLUS767E – MAY 2007 – REVISED NOVEMBER 2008

Select the timing resistor, RTSET, for the correct on-time (TON) based on KTL, as shown in Equation 36. To ensure

proper operation, the timing must be set based on the highest boost inductance (L1MAX). In this design example,

the boost inductor could be as high as 390

µH, based on line and load conditions, as shown in Equation 37.

This result sets the maximum frequency clamp (fMAX), as shown in Equation 38, which improves efficiency at light

load.

Resistor RC is selected to minimize error because of VSENSE input bias current and minimize loading on the

power line when the PFC is disabled. Construct resistor RC from two or more resistors in series to meet

high-voltage requirements. RC was also selected to be of a similar value of RA and RE to simplify the bill of

materials and reduce design costs.

Based on the resistor values shown in Equation 39 to Equation 41, the primary output over-voltage protection

threshold should be as shown in Equation 42:

Resistor RZ is sized to attenuate low-frequency ripple to less than 2% of the voltage amplifier output range. This

value ensures good power factor and low input current harmonic distortion.

The transconductance amplifier gain is shown in Equation 43:

The voltage divider feedback gain is shown in Equation 44 and Equation 45:

CZ is then set to add 45° of phase margin at 1/5th of the switching frequency, as shown in Equation 46:

Copyright © 2007–2008, Texas Instruments Incorporated

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