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HIGH-SPEED DELAY CIRCUIT

=2RC

GR0

(2)

=2(2RC+T )

(3)

402W

OUT

1/2

OPA2890

OPA890

1/2

OPA2890

750W

OPA2890

SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007

Typically, channel switching is performed either on

sync or retrace time in the video signal. The two

The OPA2890 makes an ideal amplifier for a variety

inputs are approximately equal at this point. The

of active filter designs. Figure 55 illustrates a circuit

make-before-break

disable

characteristic

the

that uses the two amplifiers within the dual OPA2890

OPA2890 ensures that there is always one amplifier

to design a two-stage analog delay circuit. For

controlling the line when using a wired-OR circuit

simplicity, the circuit uses a dual-supply (±5V)

such as that shown in Figure 54. Because both inputs

operation, but it can also be modified to operate on a

may be on for a short period during the transition

signal supply. The input to the first filter stage is

between channels, the outputs are combined through

driven by the OPA890 as a gain of +2V/V to isolate

the output impedance matching resistors (82.5

Ω in

the signal input from the filter network.

this case). When one channel is disabled, its

feedback network forms part of the output impedance

Each of the two filter stages is a 1st-order filter with a

and slightly attenuates the signal in getting out onto

voltage gain of +1V/V. The delay time through one

the cable. The gain and output matching resistor are

filter is given by Equation 2.

slightly increased to get a signal gain of +1V/V at the

matched load and provide a 75

Ω output impedance

to the cable. The video multiplexer connection (see

For a more accurate analysis of the circuit, consider

Figure 54) also ensures that the maximum differential

the group delay for the amplifiers. For example, in the

voltage across the inputs of the unselected channel

case of the OPA2890, the group delay in the

does not exceed the rated ±1.2V maximum for

bandwidth from 1MHz to 100MHz is approximately

standard video signal levels.

1.0ns. To account for this delay, modify the transfer

function, which now comes out to be:

See the Disable Operation section for the turn-on and

turn-off switching glitches using a 0V input for a

single channel is typically less than ±50mV. Where

with TD = (1/360) × (dφ/df) = delay of the op amp

two outputs are switched (see Figure 54), the output

itself. The values of resistors RF and RG should be

line is always under the control of one amplifier or the

equal and low to avoid parasitic effects. If the all-pass

other as a result of the make-before-break disable

filter is designed for very low delay times, include

timing. In this case, the switching glitches for two 0V

parasitic board capacitances to calculate the correct

inputs drops to less than 20mV.

delay time. Simulating this application using the

PSpice model of the OPA2890 allows this design to

be tuned to the desired performance.

Figure 55. Two-Stage, All-Pass Network

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