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DAC8581IPWR Datasheet(PDF) 5 Page - Texas Instruments |
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DAC8581IPWR Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 21 page  SCLK tLead t wsck t wsck t r t f -- Don’tCare BIT-14 BIT-13, …, 1 BIT-15 (MSB) BIT-0 SDIN t hi tsu DACUpdated tUPDAC 1st 2nd 15th 16th ttd CS t sck t WAIT DAC8581 www.ti.com SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 TIMING REQUIREMENTS (1) PARAMETER MIN MAX UNIT tSCK SCLK period 20 ns tWSCK SCLK high or low time 10 ns tLead Delay from falling CS to first rising SCLK 20 ns tTD CS High between two active Periods 20 ns tSU Data setup time (Input) 5 ns tHI Data hold time (input) 5 ns tR Rise time 30 ns tF Fall time 30 ns tWAIT Delay from 16th falling edge of SCLK to CS low 100 ns tUPDAC Delay from 16th falling edge of SCLK to DAC output 1 μs VDD High to CS Low (power-up delay) 100 μs (1) Assured by design. Not production tested. Figure 1. DAC8581 Timing Diagram Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DAC8581 Not Recommended For New Designs |
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